Leakage power minimization is critical to semiconductor design in nanoscale CMOS. On the other hand increasing variability with scaling adds complexity to the leakage analysis problem. In this work we seek to achieve tractability in Monte Carlo-based statistical leakage analysis. A novel approach for fast and accurate statistical leakage analysis considering inter-die and intra-die components is proposed. We show that the optimal way to select samples, to capture intra-die variation accurately, is according to the probability distribution function of total process variation. Intelligent selection of samples is performed using a Quasi Monte Carlo technique. Results are presented for benchmarks with sizes varying from approximately 5,000 to 200,000 gates. The largest benchmark with 198461 gates is evaluated in 3 minutes with the proposed approach compared to 23 hours for random sampling with comparable accuracy. Compared to a conventional analytical approach using Wilkinson's approximation, the proposed technique offers superior accuracy while maintaining efficiency. State dependence and multiple sources of variation are considered and the approach is scalable with number of process parameter variables for standard cell characterization cost. We also show reduction in sample size to meet target accuracy for computing leakage distribution due to the inter-die component only when compared to random selection of samples.

Clocks are perhaps the most important circuits in high-speed digital systems. The design of clock circuitry and the quality of clock signals directly impact the performance of a very large scale integrated chip. Clock skew verification requires high accuracy and is typically performed using circuit simulators. However in high-performance deep-submicrometer digital circuits, clocks are running at higher frequencies and are driving more gates than ever, thus presenting a higher current load on the power distribution network with the potential for substantial power grid voltage (IR)-drop. This IR-drop affects the clock timing and must be taken into account in the verification process. Since IR-drop is a full-chip phenomenon, the use of standard circuit simulation on both the clock circuitry and the power-grid is not practical. In this paper, we present a new methodology for the verification of clock delay and skew. An iterative technique is presented for clock simulation in the presence of full-chip dynamic IR-drop. The effect of IR-drop on the timing of clock signals is quantified on a small example, and demonstrated on a large chip.

Power distribution verification is rapidly becoming a necessary step in deep submicron (DSM) design of high performance integrated circuits. With the increased load and reduced tolerances of DSM circuits, more failures are being seen due to poorly designed power distribution systems. This paper describes an efficient approach for the verification of power distribution at the full-chip transistor level based on a combination of hierarchical static and dynamic techniques. Application of the methodology on practical design examples will be provided. We will also demonstrate the necessity of an analysis at the full-chip transistor level to verify the complex interactions between different design blocks based on static and dynamic effects.

Power distribution design in high-performance chips is a task that is not eased through the application of power reduction techniques. Although the average power of a high-performance design can be reduced, the peak to average power current ratio of blocks increases as a result, aggravating the challenges faced prior to average power reduction. This paper discusses the power distribution design challenge: to reliably deliver a predictable voltage to all transistors under all operating conditions. Steps in power estimation, approaches to power distribution implementation, and verification of power distribution are reviewed. The myths versus reality of power distribution design in high-performance chips are provided.