Active-matrix organic light emitting diode displays are prone to significant Vth and mobility variations in low-temperature polycrystalline-silicon thin-film transistors. A low-cost characterization of these variations can lead to a practical external calibration and simulation of the display non-uniformity. This paper proposes a generic methodology based on principal component analysis, relying on the display current levels corresponding to applied characterization images. This technique results in simultaneous characterization of the Vth and mobility for the entire active matrix. Measurement results show that taking advantage of spatial correlation leads to 100 times reduction in characterization time with less than 30% relative error.

The Latin hypercube sampling (LHS) has been used as a variance-reduction estimation tool for an efficient sampling-based variability analysis of analog circuits. For a certain estimation confidence interval, a lower number of LHS samples is needed than that of Monte Carlo due to the estimation variance reduction. In this paper, an analysis of variance decomposition of the indicator function, the yield function, reveals strong contribution of interactive terms in the variance of the yield function, leading to limited performance gain of the traditional LHS sampling. In order to improve its efficiency, two correlation-controlled LHS methods are developed to reduce the required number of LHS samples for analog circuit yield estimation.

The advanced sampling and variance reduction techniques as efficient alternatives to the slow crude-MC method have recently been adopted for the analysis of timing yield in digital circuits. However, these techniques, the Quasi-MC method and the order-statistics base estimator, are prone to bias or negligible improvement upon the crude-MC method when an early-stage timing analysis with few (10s) simulation iterations can be afforded. In this paper, these issues are studied and a control variate-base technique is developed to accurately estimate the moments of circuits' critical delays with very few timing simulation iterations. A skew-normal distribution is then used to form a closed-form cumulative distribution function of timing yield. Analysis of the benchmark circuits shows 3-10X reduction of the confidence interval ranges of the estimated yield compared to the crude-MC translating to 9-100X reduction in the number of samples for the same analysis accuracy.

The Monte Carlo (MC) simulation is a well-known solution to the statistical analysis of analog circuits in the presence of device mismatch. Despite MC's superior accuracy compared with that of the sensitivity-based techniques, an accurate analysis that involves traditional MC-based techniques requires large number of circuit simulations. In this paper, a correlation controlled sampling technique is developed to enhance the quality of the variance estimations. The superiority of the developed technique is verified by variability analysis of the input-referred offset voltage of a comparator, the frequency mismatch of a ring oscillator, and the AC parameters of an operational transconductance amplifier.

The Monte-Carlo (MC) technique is a traditional solution for a reliable statistical analysis, and in contrast to probabilistic methods, it can account for any complicate model. However, a precise analysis that involves a traditional MC-based technique requires many simulation iterations, especially for the extreme quantile points. In this paper, advanced sampling and variance reduction techniques, along with applications for efficient digital circuit timing yield analysis, are studied. Three techniques are proposed: 1) an enhanced quasi-MC-based sampling which generates optimally low-discrepancy samples suitable for yield estimation of digital circuits; 2) an order-statistics based control variate technique that improves the quality of the yield estimations, when a moderate number of samples is needed; and 3) a classical control-variate technique utilized for a variance-reduced critical delay's statistical moment estimation. This solution is shown to be effective even for a very low number of samples.

In this paper, an adaptive sampling method is proposed for the statistical SRAM cell analysis. The method is composed of two components. One part is the adaptive sampler that manipulates an alternative sampling distribution iteratively to minimize the estimated yield error. The drifts of the sampling distribution are re-configured in each iteration toward further minimization of the estimation variance by using the data obtained from the previous circuit simulations and applying a high-order Householder's method. Secondly, an analytical framework is developed and integrated with the adaptive sampler to further boost the efficiency of the method. This is achieved by the optimal initialization of the alternative multi-variate Gaussian distribution via setting its drift vector and covariance matrix. The required number of simulation iterations to obtain the yield with a certain accuracy is several orders of magnitude lower than that of the crude-Monte Carlo method with the same confidence interval.

The Monte-Carlo (MC) technique is a well-known solution for statistical analysis. In contrast to probabilistic (non-Monte Carlo) statistical static timing analysis (SSTA) techniques, which are typically derived from simple statistical or timing models, the MC-based SSTA technique encompasses complicated timing and process variation models. However, a precise analysis that involves a traditional MC-based technique requires many timing simulation runs (1000s). In this paper, the behavior of the critical delay of digital circuits is investigated by using a Legendre polynomial-based ANOVA decomposition. The analysis verifies that the variance of the critical delay is mainly due to the pairwise interactions among the principal components (PCs) of the process parameters. Based on this fact, recent progress on the MC-based SSTA, through Latin hypercube sampling (LHS), is also studied. It is shown that this technique is prone to inefficient critical delay variance and quantile estimating. Inspired by the decomposition observations, an efficient algorithm is proposed which produces optimally low L2-discrepancy quasi-MC (QMC) samples which significantly improve the precision of critical delay statistical estimations, compared with that of the MC, LHS, and traditional QMC techniques.

Recently, devices optimized for subthreshold operation have been introduced as potential construction blocks for digital subthreshold logic circuits. However, for these devices, a strong sensitivity to process variations is expected due to the exponential relationship of the subthreshold drive current and the threshold voltage. In this paper, a yield optimization technique is proposed to suppress the variability of a device optimized for subthreshold operation. By using the technique, a process/device designer can optimize a transistor for subthreshold operation in terms of the total leakage current and intrinsic delay bounds. Sample devices are optimized for 90 nm and 65 nm technologies, and Monte Carlo simulations verify the accuracy of the technique.

A new low power multiplication algorithm for reducing the switching activity through operand decomposition for Radix-8 Booth multiplier is proposed. The proposed algorithm incorporates our proposed Redundant Binary Signed Digit (RBSD) Modified Booth-3 (Radix-8) encoding scheme to generate RBSD partial product rows and low power RB Adder unit designed for accumulation and thereby circumventing the need to generate hard multiples and sign extension. Experimental results show a reduction of 21% in dynamic power consumption and at least 44% reduction in Energy Delay Product (EDP) with a penalty of 4% in area.

As CMOS technology is scaled down toward the nanoscale regime, drastically growing leakage currents and variations in device characteristics are becoming two important design challenges. Traditionally, the device-design methodology is based on finding the device parameters which minimize the leakage current while providing a minimum saturation current for the transistor. This methodology may change when variations are accounted for design. In this paper, a novel device optimization methodology is presented that incorporates variability awareness into the device-design flow such that the designed device satisfies desired bounds on total leakage, saturation current, and intrinsic delay under parameter variabilities. The technique locates the maximum-yield rectangular cube in the 5-D feasible space composed of oxide-thickness, gate-length, and channel-doping profile parameters. The center of this cube is considered as the maximum-yield design point with the highest immunity against variations. By using the methodology, four high-performance (HP) and low-power devices in 90-nm technology and one HP device in 65 nm have been designed. Monte Carlo simulations have been done to investigate the devices' performance and power metric variations and to verify their yield maximality.

The nonuniform substrate thermal profile and process variations are two major concerns in the present-day ultra-deep submicrometer designs. To correctly predict performance/ leakage/reliability measures and address any yield losses during the early stages of design phases, it is desirable to have a reliable thermal estimation of the chip. However, the leakage power sources vary greatly due to process variations and temperature, which result in significant variations in the hotspot and thermal profile formation in very large scale integration chips. Traditionally, no leakage variations have been considered during full-chip thermal analysis. In this paper, the dependence behavior among the process variability, leakage power consumption, and thermal profile construction are established to effectively extract a reliable statistical thermal profile over a die at the microarchitectural level. Knowledge of this is the key to the design and analysis of circuits. The probability density functions of temperatures are extracted while considering the leakage variations due to the gate-length and oxide-thickness variations and while accounting for the coupling between the temperature and the total leakage. Two applications of the developed analyzer are investigated, namely, the evaluation of the hotspots' relocations and the total full-chip power estimation. Finally, the accuracy and efficiency of the developed analyzer are validated by comparisons with Monte Carlo simulations.

In this paper, a novel device optimization methodology is presented that is constrained by the total leakage and the ON current of the device. The devised technique locates a maximum yield rectangular cube in a three-dimensional feasible space composed by oxide thickness, halo peak doping, and halo characteristic length parameters. The center of this cube is considered as the maximum yield design point with the highest immunity against variations. Monte-Carlo simulations show that the optimized Bulk-MOS device for 45 nm gate length satisfies the on current and leakage constraints under a variability of up to 30% in the three parameters.

Power dissipation during test is a major challenge in testing integrated circuits. Dynamic power has been the dominant part of power dissipation in CMOS circuits, however, in future technologies the static portion of power dissipation will outreach the dynamic portion. This paper proposes an efficient technique to reduce both dynamic and static power dissipation in scan structures. Scan cell outputs which are not on the critical path(s) are multiplexed to fixed values during scan mode. These constant values and primary inputs are selected such that the transitions occurring on nonmultiplexed scan cells are suppressed and the leakage current during scan mode is decreased. A method for finding these vectors is also proposed. The effectiveness of this technique is proved by experiments performed on ISCAS89 benchmark circuits.

In this paper, a new approach for reducing the subthreshold leakage current of digital circuits is proposed. It does not use a multi-threshold process technique which is more expensive. The technique which makes to use of a new variable supply voltage oscillator, combines the ideas of both Standby Leakage Control Using Transistor Stacks (SRB) and variable threshold (VT) methods. In this technique compared to the Leakage Control Using Transistor Stacks method, the subthreshold current decreases three times. In addition, leakage current monitor (LCM) and its related circuits which are used in VT techniques are not required here. This makes the proposed technique more power and area efficient.