Testing large circuits requires compression of test patterns before transferring them to the tested circuit and decompression on board. The compression and decompression mechanism may be built according to the linear block code rules. Broadening the decompressor structure search space to those using nonlinear block code is possible. Nonlinear block codes outperform their linear counterparts' compression ability. Their usage is limited due to the intricate search process. The code words' interconnectedness is difficult to exploit in the code word creation process as too many mutual dependencies exist among the code word bits. For this reason, random and partially random code word search methods were investigated in the past. This paper proposes two fully deterministic nonlinear code construction approaches. The obtained codes are significantly more efficient and easily scalable than the linear ones. We demonstrate their efficiency on codes with the number of specified bits equal to two, three, and four. The proposed methods may be used to create extensive codes, which are unachievable for previously published methods due to the explosion of computation time.

This paper deals with extending linear compression codes by nonlinear check bits that improve the usability of decompressed patterns for testing circuits with more inputs. The earlier works used a purely random or partially random search of the nonlinear check-bits truth tables to construct the first nonlinear structures. Here, we derive deterministic rules that characterize the relationship among the nonlinear code check bits. The efficiency of the rules is demonstrated on different codes with the number of specified bits equal to three. The code parameters obtained after applying the rules overperform the parameters of the linear codes. Keeping the restrictions makes the search for the check bit truth tables faster and more efficient than can be got by a simple random search. The reached nonlinear block code (136,5,3) is the most efficient code among other loose compression codes.

Test pattern compression techniques reduce the amount of transferred data while decompressed pattern flexibility remains high. The flexibility can be measured by the guaranteed number of specified test pattern bits, equal to or greater than the number of care bits in the pattern. This paper addresses the problem of test pattern compression and decompression using nonlinear codes. Test patterns can be encoded using a linear code that leads to an XOR network that decompresses the compressed patterns transferred from a tester. This XOR network can be completed or replaced by a standard (nonlinear) combinational network with substantially improved compression efficiency. The problem of finding the code was formulated as a clique cover problem. This approach’s tight throat lies in computational complexity and the needed memory capacity to temporarily retain intermediate results of clique coverage search attempts. The paper proposes a method that substantially reduces the computational time to get a robust nonlinear code with decompression ability. It shows that random search algorithms cannot reach the code parameters obtained by a restricted iterative search proposed in the paper. Additional knowledge concerning the check-bit truth table characteristics was used to avoid unsuccessful investigations. The proposed decompressor schemes have higher efficiency than till now known decompressor constructions. On the other hand, finding other heuristics that provide efficient codes for a broader class of code parameters is challenging than the proposed solution.

It was found that the linear binary codes can be extended by a relatively high number of nonlinear check bits in such a way that the code words preserve the value of the maximum number of independently specified bits from the original linear code words. These extended nonlinear binary codes can be used for pattern compression and decompression. The number of scan chains loaded in parallel from the sequential decompressor may be increased while the number of specified bits is kept. The nonlinear structures guarantee the number of independently specified bits within the whole decompressed test pattern independently on the scan chain clock cycle for a substantially higher number of parallel scan chains than the linear decompressors while the number of bits transferred from the tester is kept. We proposed an algorithm that finds the appropriate nonlinear modification circuit of the sequential decompressor and verifies the test pattern quality for different numbers of care bits in a test pattern.

Test patterns are transferred from the tester to the circuit under test in a compressed form as it minimizes test access mechanism bandwidth and transfer time. It was found that nonlinear binary codes could be useful for encoding test patterns in a similar way as linear ones and the compression efficiency may be higher. The key important characteristics of the nonlinear codes are that the number of codeword bits may be higher than it is for the linear code words while the number of specified bits is preserved. The nonlinear binary codes can be used in test pattern decompressors. It causes better encoding characteristics can be obtained for a higher number of parallel scan chains comparing with linear codes. In this paper, we propose a relatively fast heuristics that can be used for finding the nonlinear function truth tables guaranteeing the required number of specified bits and enables hardware overhead minimization. We quantify the benefits and costs of decompressors with nonlinear codes and verify the benchmark circuit test pattern encoding efficiency.

The paper is a contribution to the 50th anniversary celebration of the International Test Conference (ITC) and its Global Test Forum (GTF), which honors the geographic breadth of the test community and highlights the global reach of ITC during the past 50 years. It covers the past, present, and future of the International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), a symposium which belongs to prominent test technology related events initiated and supported by the ITC.

The linear binary codes can be extended by a relatively high number of nonlinear check bits in such a way that the code words preserve the value of the maximum number of independently specified bits from the original linear code words. A substantial improvement can be achieved in the field of sequential pattern compression using these nonlinear codes. The number of scan chains loaded in parallel can be increased while the number of specified bits is kept. We propose an algorithm that finds the appropriate nonlinear modification circuit structure and verifies the test pattern quality for different numbers of care bits in a test pattern.

This paper describes a test response compaction system that preserves diagnostic information and enables performing a test-per-clock offline testing. The test response compaction system is based on a chain of T flip-flops. The T flip-flop signature chain can preserve the information about the position of the first occurrence of the erroneous test response and the information about the clock cycle when the erroneous test response occurred. This information can be used for diagnostic purposes. The paper discusses the possible benefits and limitations of the proposed test pattern compaction scheme. The influence of multiple errors on detection and localization capability of the compaction system and hardware overhead is discussed in the paper as well.

In this paper, we show that the binary linear codes can be extended by a relatively big number of check bits in such a way that the code words preserve the value of a maximum number of independently specified bits from the original linear code words. It can improve pattern compression and-or pseudo-exhaustive testing. Existing linear compression and testing techniques adopt linear codes either for pattern expansion in the decompressor or for pattern generation. The minimum code distance of the dual linear code determines the encoding efficiency, the greater distance causes the bigger maximum number of independently specified bits on the decompressor outputs. While keeping the number of specified bits for longer code words the extended codes provide a possibility of feeding more parallel scan chains with the decompressor output bits. In the case of pseudo-exhaustive test pattern generators, the extended nonlinear codes guarantee an existence of the universal pseudo-exhaustive test set with better parameters than can be obtained for linear test pattern generators. We compare the properties of the extended non-linear and linear codes and demonstrate the effectiveness of the decompressors using these codes.

Usually, test pattern decompressors with dynamic reseeding are reset before starting a new test pattern decoding. The first few scan chain slices are then filled with test vectors that have lower decodability as the number of free variables is limited by the test access mechanism bandwidth. We have found that it is possible to increase the number of free variables in the equations describing the care bits encoding by fast creating and wide spreading as many as possible independent linear combinations of the tester bits and using them for the scan chain loading. We propose a decompressor combining a combinational linear decompressor and an LFSR like automaton that effectively distributes the free variables within the test pattern. The proposed test pattern decompressor outperforms the de-codability of other decompressors with similar hardware overhead and it reduces the test time due to a possible reduction of the decompressor preloading.

We propose a sequential test pattern decompressor enabling dynamic reseeding. It reduces dependency between the decompressor output bits during the first few clock cycles after decompressor reset. Due to this fact, a lower number of clock cycles is necessary to be performed in order to encode test patterns. We evaluated features influencing the decompression quality and the hardware overhead for different decompressor principles. According to the evaluation results, we propose a decompressor combining a combinational linear decompressor and an linear feedback shift register (LFSR) like automaton, we place the combinational decompressor on the LFSR inputs. We demonstrate that due to this arrangement the combined decompressor can be used without any phase shifter and/or state skipping ability of the LFSR. We have experimentally verified that adopting the proposed decompressor structure improves test coverage, saves the hardware resources and shortens the test application time.

In this paper, we present an investigation of the suitability of the impulse ultra-wideband (I-UWB) technology for neural recording systems. A fully-digital I-UWB transmitter, implemented in a 65 nm CMOS, is connected to a miniature antenna and packaged in bio-compatible material. Two experimental telemetry configurations are considered. The head of a domestic pig is used to mimic a neural activity monitoring system that is conventionally implanted in swine. Three main objectives are accomplished (1) the strength of the UWB signal after propagating from the cranial cavity through the pig's skull and skin is measured for several separation distances; (2) a statistical model of large-scale signal fading is developed; and (3) the developed model is used to evaluate the system performance with recently published UWB receivers.

The paper discusses possibilities of rearranging test decompress or internal structure and linking its outputs with the parallel scan chain inputs in order to obtain better compression efficiency while the hardware overhead is not increased. We have experimentally verified that the controllability of decompress or outputs can be used as a simple and easily computable measure of the decompress or efficiency. Based on this observation we have developed a procedure that chooses a sub optimal LFSR outputs and parallel scan chain inputs interconnection. The procedure proposes a permutation of the scan chain inputs so that the scan chains that are fed with patterns with higher number of care bits are linked with the highly controllable decompress or outputs. We have experimentally verified on the benchmark circuits that adopting the proposed strategy improves the compression efficiency.

The paper describes a modified Smart BIST methodology that provides test data volume compression. The test equipment is easily applicable because it is based on the standard scan methodology. The method is based on continuous LFSR reseeding decompression that is used in such a way that it enables lockout escaping within a small number of clock cycles. It requires a separate controlling of the LFSR decompressor and the scan chain clock inputs. We propose a modified LFSR with state skipping for the pattern decompression that does not require a phase shifter and saves hardware. A pattern encoding algorithm minimizing the number of clock cycles of the decompressor needed for decoding test patterns is also proposed. The parameters can be tuned in such a way that the method provides similar data magnitude reduction and decompressor hardware overhead as other test compression methods but it substantially reduces test time, number of tester channels and hardware overhead. Experimental results of benchmark circuit testing show that the modified Smart BIST methodology provides unreduced test coverage, low hardware overhead and short test sequences.

The paper presents a test-data volume-compression method which reduces test time and hardware overhead by test pattern broadcast into parallel scan chains. The proposed hardware enables efficient test pattern decompression and test response compaction. It uses a XOR-less structure instead of ring generators for test pattern decompression. Decompressed test vectors are obtained from the previously generated ones by simple shift operations only. The compression algorithm can search in a wider pattern space when finding the best fitting decompressor seed sequence because of this arrangement. The faults of basic gates can be covered by the patterns easily obtained in the decompressor during several clock cycles as a majority of faults can be tested by patterns that differ in a few shift operations only. The paper describes a test pattern decompressor hardware including its controller. The decompressor reduces the number of flip-flops containing information about previously generated pattern by test pattern broadcast into parallel scan chains. The memory requirements, test time and hardware overhead are compared with the parameters of circuits designed by the industrial test compression and compaction tools. The hardware realization can be modified according the required tradeoff between the complexity of test sequence control and the hardware overhead.

This paper presents a design flow that allows relocation of reconfigurable modules on Xilinx FPGAs using dynamic partial reconfiguration (DPR). Relocation of these modules is performed without requirements of re-implementing the design. The article describes the relocation procedure based on modifications of major address of the partial configuration bitstream. This approach allows using single partial bitstream for multiple areas in FPGA device. It reduces a number of partial bitstreams stored in memory, saves the implementation time and it can increase dependability of the system. The proposed flow is demonstrated on a simple example with multiplier and adder locations mutually exchanged.

The paper deals with the problem of test data volume, test application time and on-chip test decompressor hardware overhead of scan based circuits. Broadcast-based test compression techniques can reduce both the test data volume and test application time. Pattern overlapping test compression techniques are proven to be highly effective in the test data volume reduction and low decompressor hardware requirements. This paper presents a new test compression and test application approach that combines both the test pattern overlapping technique and the test pattern broadcasting technique. This new technique significantly reduces test application time by utilizing a new on-chip test decompressor architecture presented in this paper.

In this paper we evaluate the application dependent FPGA (Field Programmable Gate Array) test method which uses an ASIC BIST (Application Specific Integrated Circuit Built-in Self-Test) techniques and tools and efficiently utilizes the properties of nowadays FPGA devices, such as the partial runtime reconfiguration. The method splits the tested circuit and then uses partial reconfiguration to change the role of the partitioned modules, which may act as testers or as response analyzers. Circuit partitions are translated to an ATPG (Automatic Test Pattern Generator) readable format and the deterministic test vectors are generated. The compression tool is used to compress test patterns, thus it is not required to create additional test access interfaces or to use multiple reconfigurations. We show that the usage of the method reduces test time and memory requirements and it leads to good test coverage results. Each step of the design flow is described and evaluated in detail as well as the experimental results and the hardware.

This paper describes an algorithm, which utilizes a test data compression method based on test vector overlapping to compact and compress test patterns. The algorithm takes deterministic test vectors previously generated in an ATPG and compresses them by reordering and overlapping them. It is able to speed up the test generation process by using distributed ATPG processing and compress test data for various fault models. Independency of the algorithm on used ATPG is discussed and verified, the compressor is able to cooperate with industry workflow tools using Verilog and STIL formats. The compressor preprocesses the input data to determine the degree of random test resistance for each fault. This optional step allows to rearrange the test vectors more efficiently and results to 10% compression ratio improvement in average.

A method and architecture for synchronization of Fault-Tolerant system implemented in FPGAs is proposed. It is based on repairing faulty units and transferring of the fault-free state of the system to the unit under repair. Its architecture is based on the previously designed model which is extended for usage in more complex systems. The proposed method was implemented on an FPGA and the experimental architecture with an analysis of the results is given.

Application dependent FPGA testing can reduce time and memory requirements comparing with the tests that exercise complete FPGA structure. This paper describes a methodology of FPGA testing that does not require reconfiguration of the tested hardware and thus it preserves conditions that caused erroneous behavior of the FPGA during its function. We show that the tested part of the FPGA can be efficiently tested by deterministic test patters even in case if we have no precise information about the internal FPGA structure. It is too hardware consuming to store uncompressed deterministic test patterns on the FPGA. From this reason we propose to compress the deterministic test patterns with the help of COMPAS - a compression system that uses scan chains for pattern decompression. COMPAS is well suited for current FPGAs as they can store the scan chain content in the LUT based shift registers. The COMPAS test compression system is based on test pattern overlapping, we propose an improved version of it. Application of overlapped test patterns requires additional shift registers for saving test patterns during test response recording into the internal scan chains. The neighborhood of the tested part of the FPGA can be dynamically reconfigured into shift registers and ORA. The shift registers contain compressed test sequence and allow fast test pattern decompression. Experimental results given in the paper demonstrate efficiency of the proposed FPGA testing method.

Tests that exercise complete FPGA resources are often more time and memory consuming than application dependent tests due to the high number of reconfigurations required for complete test. Presented application dependent test does not require reconfiguration of the tested hardware, thus it preserves conditions that led to the erroneous behavior of the FPGA device. The test method saves time and memory requirements of the test by storing compressed test patterns into the internal structure of the FPGA. The patterns are obtained with the help of the improved COMPAS algorithm – compression system based on test pattern overlapping. The COMPAS requires unused scan chains for the test pattern decompression. This is well suited for nowadays FPGAs which contain high number of LUT based shift registers. The neighborhood of the tested circuit is dynamically reconfigured into TPG and ORA. The TPG contains compressed test patterns which allow fast test pattern decompression. The paper demonstrates efficiency of this approach on experimental results.

We present a new concept of the test method for FPGA devices. Instead of being focused on structural test of the device, the method tests logic and interconnection resources of the FPGA, that are actually used by implemented circuit. The method is based on reconfiguration ability of nowadays FPGAs and utilizes test vectors originally created for ASIC circuits. We present an idea of circuit partitioning and a transcription scheme, that converts the FPGA netlist to the ASIC one. Preliminary results of test patterns efficiency on transformed benchmark circuits are presented.

The backtrace algorithm lies at the core of many applications, including automatic test pattern generation (ATPG). This paper describes and evaluates an approach for accelerating the backtrace algorithm using conflict-based on-line learning. This approach gets high performance due to large amounts of fine-grain parallelism in the implication process. Architecture of circuits performing backward determination of all input vectors to a given output one is presented as well. The results of this new method are compared with HW implementation of the basic backtrace algorithm proposed recently. The experimental results have been obtained for the ISCAS’85 benchmarks - for those largest, the average growth of an area overhead is about 49 % and the average speed up is about 25 %.

A method of pseudoexhaustive test pattern generation is proposed that is suitable above all for circuits using random access scan. Two linear feedback shift registers are used to generate scan addresses and test patterns to be scanned into these addresses. It is shown that the method gives better results than random testing.>