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EDBT 2026 Demo / reviewers in the wild / expert

John J. Lenahan

dblp:48/5876 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1980
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Performance modeling and evaluation · 50% Parallel and multicore computing · 50%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing › multiprocessor system
loosely coupled multiprocessor		 0.011980
Performance of Cooperative Loosely Coupled Microprocessor Architectures in an Interactive Data Base Task · IEEE Trans. Computers 1980
Performance modeling and evaluation
workload characterization		 0.011980
Performance of Cooperative Loosely Coupled Microprocessor Architectures in an Interactive Data Base Task · IEEE Trans. Computers 1980

Methods — techniques the papers use, named apart from their topics

experimental performance study · 0.0
YearPublicationVenuePosition
1980 Performance of Cooperative Loosely Coupled Microprocessor Architectures in an Interactive Data Base Task
abstract
Continuing technological advances in single-chip intelligence and storage cell density, and in bulk store performance provide increasing opportunities to construct multiple microprocessor systems. The objective of this experimental study was to explore the performance of selected system architectures in a manner sufficiently detailed, quantitative and realistic to 1) contribute to our understanding of the fundamental behavior of such systems and 2) permit practical designs to follow from the results.
John J. Lenahan, Fergus K. Fung
 IEEE Trans. Computers1