Software-defined networking (SDN) has revolutionized network infrastructure, offering programmability to meet evolving network demands. However, the fixed-function nature of the packet scheduler in current network equipment impedes the exploration of scheduling policies within a programmable network environment. This paper proposes a novel methodology to implement rank-based programmable schedulers in programmable BMv2 switches expressed with the network-specific programming language (P4). A proposed custom networking environment facilitates the study and evaluation of various scheduling policies. This environment is used to implement 20 different scheduling and shaping policies to identify the required language constructs and components needed to express these policies with the P4 language efficiently. Our experiments reveal that specific scheduling policies do not seamlessly align with a previously proposed architecture for rank-based scheduling policies. Thus, we propose rank-based versions for five previously reported scheduling policies, making them efficiently implementable in any rank-based schedulers and programmable network equipment. The reported results confirm that the rank-based versions of these scheduling policies accurately replicate the behavior and performance of the original policies, with a maximum error of 0.5% in the resulting flow completion times (FCTs).

Software-defined Networking (SDN) introduced the decoupling of control and data forwarding planes. Despite advances in the programmability of SDNs, there remains a strong need for a fully programmable packet scheduler in the data plane. In this context, the ability to adapt to various traffic patterns and the expressiveness of schedulers are of paramount importance. This paper introduces the Dynamic Ranking Push-In-First-Out (DR-PIFO), as an algorithmic model that can be used to develop programmable packet schedulers based on PIFO queues. The DR-PIFO is a highly expressive model, capable of expressing a wide range of work-conserving, non-work-conserving, and hierarchical scheduling algorithms. Additionally, its dynamic ranking capabilities allow for real-time updates to the packet’s priority within the scheduler. The proposed solution also performs error detection in the departure order of packets, which is essential to avoid starvation in strict priority scheduling. These features are crucial when implementing popular scheduling algorithms such as the pFabric. The DR-PIFO is evaluated through its algorithmic properties and by implementing two distinct case studies. Its performance is further evaluated by incorporating it as an external module, written in a high-level language, and integrating it with software switches implemented using the P4 language. The results illustrate the superior expressiveness of DR-PIFO over state-of-the-art models such as PIFO and PIEO and confirm that it is an algorithm-agnostic model. Thus, DR-PIFO represents a promising solution for implementing more fully programmable packet schedulers in SDNs, with the potential to improve performance and adaptability.

Bugs in network devices translate to financial losses for the service providers and degrade the quality of experience for the users. Simulation tools cannot guarantee complete fault coverage as bugs can manifest at any time in live hardware. To mitigate these issues, we propose a novel hardware/software (HW/SW) co-verification tool that targets programmable dataplane network devices. The system integrates cycle-accurate software simulation with a hardware implementation. For the software simulation, open-source tools such as CocoTB and GHDL were used. The Design Under Test (DUT) and our test interfaces are embedded in programmable hardware. Data from the software can be inserted and then extracted in real-time from the input/output (I/O) ports of the DUT. To achieve this functionality the hardware design uses data insertion and extraction blocks which also support assertions. For the hardware implementation, reported experiments have been conducted on a NetFPGA-SUME platform. When a packet flows through the NetFPGA and triggers an assertion, the data present in the DUT at that time can be captured, and sent back to the simulator for further analysis and replay. Each of our design block consumes less than 1% of the available resources on the FPGA.

In this work, we propose a clock scheduling algorithm that is used to mitigate the effects of clock skew that can arise from thermal run-time variations. Depending on the amount of skew, the algorithm selects a different minimum delay tolerance value in order to correct the skew problems, without the performance penalties that are associated with static worst-case scheduling policies. The design was first implemented in MATLAB to obtain the data needed for the clock scheduling. Then, it was implemented in VHDL and synthesized using Xilinx's Virtex-II Pro technology library. Back annotated simulations prove the functionality of the proposed design. The adaptive scheduling scheme achieves up to 60% latency reduction, in our implemented example, compared to a static scheduling scheme.

In this paper, the authors propose two high-speed variable rate clock generator circuits that can synthesize frequencies which are fractional multiples of an input clock. The designs can switch between frequencies in a glitch-free manner, within a single clock cycle. In response to an N-phase reference clock, the first circuit can generate a clock of up to N times the reference frequency, whereas the second solution can generate up to N/2 times that frequency. The available synthesized frequencies are given by frefmiddotN/M , where M can be any integer greater than or equal to 1, depending on the circuit. The solutions were coded in VHDL, synthesized, placed and routed in TSMC's 180nm CMOS technology. Simulations using the extracted layout show that the proposed designs can operate with a reference frequency of up to 400MHz, yielding a maximum output clock of 4times the reference, or 1.6GHz. The designs were also validated with an implementation on Xilinx's Spartan 3 FPGA device.

In this paper, an algorithmically defined buffer and ring oscillator design for low energy applications is proposed. The goal of the algorithm is to easily converge to a low energy solution while the system maintains constant speed and full swing at a given supply voltage, irrespective of the capacitive load. The experimental circuit is a 980MHz oscillator operating from a 0.8V supply, driving a 1pF load, designed using a 0.18mum TSMC CMOS process technology. A comparison to the well known minimum delay tapered buffer, using an exponential horn designed independently of the oscillator, is done. The comparison shows that our algorithm produces a 3.7-3.9 times improvement in terms of power, energy, and energy delay product (EDP) metrics, and 14.6 times improvement in terms of the energy area product (EAP)