International audience

Recharging the battery of a biomedical implant has been a major topic for several decades. Access to the device requires an often heavy surgical intervention involving huge costs for the health system, not to mention the discomfort suffered by the patient. Hence, remotely supplying the implant is a more than desirable solution. In this context, a miniaturized magnetoelectric transducer working in the ultrasound range has been proposed to remotely power a biomedical implant. Here, a monolithic integrated chip is proposed to efficiently extract the transducer energy. It includes an ultra-low-power, inductor-less, self starting up power management unit. Energy extraction is performed by an active voltage doubler with an efficiency of 88.3 % while extracting 626 μW. A Maximum Power Point Tracker ensures a maximum efficiency keeping the transducer at its maximum power point. Then, the voltage is boosted with a cross-coupled charge pump and the energy is stored in a reservoir before supplying the payload in short periodic bursts through a Low Dropout voltage regulator that may provide up to 280 μJ/burst.

This article presents a universal implementation of a Maximum Power Point Tracking solution for a kinetic energy harvester composed of an electrostatic transducer in association with a capacitive charge pump. The proposed MPPT solution, based on "perturb and observe" method, selects automatically and in real time the optimal electrical state of the charge pump (the voltage of the reservoir capacitor), so to guarantee the maximum of the extracted power under current operation conditions. The proposed solution is implemented alongside a Power Management Integrated Circuit (PMIC) which offers a possibility to control the reservoir's voltage.

In this paper, we study networks of coupled oscillators applied to the distributed synthesis of clock signals for large systems-on-chip. The oscillators are implemented as interconnected all-digital phase-locked loops (ADPLLs), which are asynchronous control systems. We address the issue of modelling, synchronization and stability of both a single ADPLL and interconnected ADPLLs. We prove that the stability domain is universal for large Cartesian networks, and it related to the domain for a single ADPLL. We show that within the stability domain the network synchronises to the reference signal both in frequency and phase. A hardware verification of Cartesian networks is presented, and it is consistent with our theoretical findings. The proposed design may be useful for multiples engineering and physics applications, including clock generation, distributed computations, beamforming, and other applications, where the control over time synchronicity is crucially important for the system performance.

In this paper we present an autonomous Power Management Integrated Circuit PMIC for an electret-biased electrostatic kinetic energy harvester with a Bennet's doubler conditioning circuit. The circuit is designed in high voltage 0.35μm standard bulk CMOS technology. It supplies a low voltage load from the energy extracted from a high voltage transducer. The circuit is provided with a “cold start” mechanism and with a “safe mode” (Recovery) feature that permits to the system to stay active (awake) for a longer time after external vibrations stop temporarily. An ultra-low static power hysteresis comparator is designed for a specific control of the capacitive transducer's conditioning circuit. The autonomy of the system is ensured by a voltage regulator that supplies the internal blocks of the circuit with 1.1 V. The measured maximum end-to-end efficiency of the implemented system is 75% when the available input power was of 80 μW.

In this paper, we introduce a statistical approach for studying a special class of nonlinear dynamical systems such as ADPLLs and ADPLL networks, where the process driving the adjustment of the DCO frequency can be seen as ΣΔ modulation. We showed that, by applying the Frobenius-Perron operator to the governing equation, it is possible to find the invariant probability density which is valid for dynamically changing input of Σmodulator. By using this, we show that the average behaviour of the corresponding complex system can be dramatically simplified and studied analytically.

The paper aims at stimulating a discussion on the prospect and potentiality of open source electronic design automation tools and open source hardware. We discuss the benefits and motivation, as well as the expected difficulties and shortcomings. Finally, we provide a representative list of efforts as of today specifically for analog and mixed-signal circuits and systems design and prototyping.

This work presents a rigorous electrical analysis of charge-pump conditioning circuits for capacitive energy converters (CEG) with built-in bias voltage. The subsequent implications on the selection of the optimal conditioning circuit are also presented. In particular, the determining role of the application context and constraints on the optimal conditioning circuit choice is discussed. This context is defined by the transducer's capacitance variation amplitude, by the value of the built-in bias of the transducer, and by limitations on the operating voltages across the circuit elements and the transducer.

In this paper, we propose the model of a network consisting of All-Digital Phase-Locked Loop Network in application to Clock-Generating Systems. The method is based on a solution of a system of non-linear finite-difference stochastic equations and allows us to perform high speed simulations of a distributed Clock Network on arbitrary topology. The result of our analysis show a good agreement with experimental measurements of a 65nm CMOS All-Digital Phase-Locked Loop Network.

In this paper we consider a network of phase oscillators. We develop the equations that model the time evolution of the phase of each oscillator in the network. The oscillator represents a modified Kuramoto oscillator and in this study we discuss how these modifications are obtained. In the context of this study, we use this network to model a network of PLLs for distributed clock applications. We analyse analytically and numerically the synchronisation modes of this system for different types of the coupling function. We show that depending on the properties of the coupling function, the network displays either multiple coexisting synchronisation modes or only a single synchronisation mode. While in the context of clock generation, multiple synchronisation modes coexisting in the system at the same parameters are a parasitic phenomenon. However in the context of other application such as associative memory models, mode-locking can be seen a useful phenomenon. The results provide a deeper understanding of globally synchronised clock networks with applications in microprocessor design.

The aim of this paper is to formalise the term “complexity” in the context of modern microelectronics, propose the definitions of key terms and discuss a case study. Our aim is to show that the term “complex system” is implicitly related to the design of electronic systems.

Transitions to chaos in one-dimensional maps are known to occur in a universal fashion. This transition can be described symbolically by a sequence of words known as the U-sequence. In this work we investigate the appearance of this U-sequence in a class of electronic oscillators that describe the dynamics of electrostatic vibration energy harvesters. We show how the method of symbolic dynamics is applied to systems described by ODEs and further, we investigate why the U-sequence is not fully followed by this class of oscillators that contain a non-conservative damping force.

In this paper, we overview the sources of nonlinearities and the methods of analysis for electrostatic (capacitive) vibration energy harvesters by the example of an energy harvester employing a charge pump base conditioning circuit. Electrostatic vibration energy harvesters are devices that contain mechanical resonators driven by ambient vibrations and coupled with conditioning electronic circuits through a capacitive transducer. These devices are characterised by internal and external nonlinearity and complexity and can display irregular behaviour. We give an overview of the capacitive conversion mechanisms and discuss the nonlinear techniques that can be employed for the analysis of nonlinear vibration energy harvesters.

This paper presents an overview of problems related to electronic conditioning of capacitive transducers used for the kinetic energy conversion. It proposes a methodology for the system-level and circuit-level design of conditioning electronics for electrostatic energy harvesters so to comply with the requirements of realistic applications: long-lasting operation, self-calibration, low consumed power and the implementation using the integrated circuit CMOS technology. An original architecture of a self-calibrating conditioning circuit is proposed. The paper gives a review of main design challenges related to this architecture, explains the motivation of the technology choice, provides insight into critical blocks and presents intermediate results of design.

In this review paper, we define and discuss the concept of complexity for heterogeneous systems. Due to the current progress in fabrication technology, modern micro-scale integrated systems may have a large number of interacting elements. Each of those elements not only displays its own dynamical properties, but also, in the most general case, can be nonlinear or can belong to different physical domains. We consider two different examples of systems that are complex in the terms we use in this paper. The first example is a network of oscillators and is heterogeneous since it is a mixed-signal system. The second example is an electrostatic vibration energy harvester, a micro scale system combining elements from the mechanical and electrical domains. In both cases we discuss the challenges that arise at the stage of the system design.

Vibration energy harvesting is a technique for the generation of electricity from ambient vibrations. Electrostatic vibration energy harvesters (e-VEHs) are particularly compatible with microtechnology and can serve as a source of energy for autonomous microsystems. E-VEHs require conditioning electronics to effectively sequence different phases of energy conversion. One of the most promising circuits for e-VEHs is the charge pump, presented here with a resistive return circuit. E-VEH as a system is composed of a mechanical resonator coupled with a conditioning circuit and is strongly nonlinear. We discuss different models of this system and show how steady-state oscillations of the system can be analysed. In order to do so, the system is represented as a nonlinear oscillator and a perturbation technique, such as the multiple scales method, can be applied.

Synchronization is an issue of significant importance in large-scale, distributed and high-speed systems. Traditional globally synchronous approach is no longer viable due to severe wire delay. Solutions such as “Globally Asynchronous, Locally Synchronous (GALS)” approaches suffer from metastability risk limiting their use in many-core SoC for critical applications, such as aerospace, military or medical equipment. This paper presents a distributed clock generator based on a network of oscillators. A great advantage of this architecture is its high stability and immunity to perturbations. This architecture also makes possible to design large fully synchronous SoC. A 10×10 network supplying clock sources for 100 clock domains has been modeled in VHDL and is under design in silicon. Simulation results show ± 40 ps peak-to-peak phase error between two neighboring clock signals and ± 50 ps between two clocks in distance.

The aim of this paper is to study an electrostatic vibration energy harvester that utilises a nonlinear resonator. A vibration energy harvester represents a system where a mechanical resonator driven by ambient vibrations is coupled with a conditioning electronic circuit, which acts as a damper and converts mechanical energy into electrical. If a nonlinear resonator is embedded into the conditioning circuit, nonlinearity will appear from both mechanical and circuit components of the system. We expand the analytical approach that we developed in our previous works to the case of combined mechanical and circuit nonlinearities. This allow us to analyze steady-state behavior and compare it with the linear case. In addition, we discuss a specific nonlinear phenomena that is introduced by the discontinuity of the system - the sliding bifurcation. We show that the onset of steady-state quasi-harmonic oscillations occur through the disappearance of sliding motion.

In this review paper, we discuss the principles of electrostatic (capacitive) vibration energy harvesters and nonlinear techniques that can be applied to improve the performance of harvesters. Electrostatic vibration energy harvesters are devices that contain mechanical resonators driven by ambient vibrations and coupled with conditioning electronic circuits through a capacitive transducer. While the devices can be fabricated using MEMS technology and miniaturised, internal and external nonlinearity and complexity can lead to irregular behavior and impede the analysis of the devices. In this review we give an overview of the capacitive conversion mechanisms, discuss the basic triangular energy conversion cycle in detail and survey the nonlinear techniques that can be employed in these systems.

In this paper, we present an analysis of an electrostatic vibration harvester operating in the constant-charge mode. The goal of the study is to bound regions of control parameters where the system displays steady-state harmonic oscillations as required for practical use. We show how the system can be presented as a nonlinear oscillator and analysed employing the multiple scales method, Floquet theory and Lyapunov exponents. We determine the conditions for the onset of steady-state oscillations, the period doubling bifurcation and transition to chaos. This allows us to bound regions of control parameters where the system displays desired regular oscillations and, therefore, to identify maximal harvestable power for a particular architecture.

This paper presents an FPGA platform for the design and study of network of coupled All-Digital Phase Locked Loops (ADPLLs), destined for clock generation in large synchronous System on Chip (SoC). An implementation of a programmable and reconfigurable 4×4 ADPLL network is described. The paper emphasizes the difference between the FPGA and ASIC-based implementation of such a system, in particular, implementation of digitally controlled oscillators and phase-frequency detector. The FPGA-implemented network allows studying complex phenomena related to coupled ADPLL operation and exploiting stability issues and nonlinear behavior. A dynamic setup mechanism has been proposed for the network, allowing selecting the desirable synchronized state. Experimental results demonstrate the global synchronization of network and performance of the network for different configurations.

The search for compact autonomous devices has been increasing in the microelectronics industry. These devices have the capacity to generate their own energy in order to be charged. One of the ways of harvesting environmental energy for charging such devices is by using mechanical vibrations through the use of variable capacitor. Taking this principle a basis, this work presents a behavioral analysis of a system model of harvesting vibratory energy for low power, made up of a circuit which includes a variable capacitor and a piezoelectric transducer. An architecture of a circuit which improves the ratio “amount of harvested energy - circuit area” comparing with conventional architectures is presented. The conventional circuit harvested a maximum power of 4.5μW whereas the circuit with the new architecture harvested a 6.25 μW power. The paper shows a use of a piezoelectric generator providing initial power and compensating the leakage losses in the capacitors.

This paper presents a new architecture of bang- bang phase frequency detector based on standard cells. The pro- posed architecture presents advantages in terms of compatibility with fully-automated design flow of digital circuitry compared with other architectures. The metastability failure is also studied. The reliability of this architecture is approved by simulation results in CMOS65 nm.

This brief addresses the problem of clock generation and distribution in globally synchronous locally synchronous chips. A novel architecture of clock generation based on network of coupled all-digital PLLs is proposed. Solutions are proposed to overcome the issues of stability and undesirable synchronized modes (modelocks) of high-order bidirectional PLL networks. The VLSI implementation of the network is discussed in CMOS65 nm technology and the simulation results prove the reliability of the global synchronization by the proposed method.

This paper presents a CMOS 1.1-2.8 GHz 10 bits digitally controlled oscillator (DCO) for high speed clocking of SoCs. The DCO includes only 269 tuning cells, which is possible thanks to an original algorithm based on weighted combined thermometer code, used for the DCO frequency control. The control circuit of the DCO includes only binary-to-thermometer decoders: that was possible with the proposed technique of virtual extension of number of the DCO ring. It was implemented in 65-nm CMOS technology, with semi-custom layout design allowed to optimize the area on silicon. The design was validated by transistor-level ELDO extracted schematic simulation. Oscillator shows a good linearity in the frequency tunning range, with average power consumption 6 mW/GHz with 1.1 V supply voltage. Typical phase noise with 1 MHz offset and 2 GHz carrying frequency is -86.12 dBc/Hz.

In this paper, we describe an architecture of a distributed ADPLL (All Digital Phase Lock Loop) network based on bang-bang phase detectors that are interconnected asymmetrically. It allows an automatic selection between two operating modes (uni- and bidirectional) to avoid mode-locking phenomenon, to accelerate the network convergence and to improve the robustness to possible network failures in comparison to simple unidirectional mode.

This paper presents the results of modeling of a mixed non-linear, strongly coupled and multidomain electromechanical system designed to scavenge the energy of ambient vibrations and to generate an electrical supply for an embedded microsystem. The system is operating in three domains: purely mechanical (the resonator), coupled electromechanical (electrostatic transducer associated with the moving mass) and electrical circuit, including switches, diodes and linear electrical components. Although only linear networks can be properly modeled in SystemC-AMS, we propose a technique allowing modeling of electrical networks including non-linear components (diodes) as well as time-varying capacitors. The whole system was modeled using two solvers of SystemC-AMS simultaneously: the one allowing TDF (timed data flow) modeling and the one allowing LIN ELEC (linear electrical) circuit analysis. The modeling results are compared with VHDL-AMS and Matlab Simulink models.

For the past few years, the mobile phone market has been facing fast growth. However, the first generations of mobile telecommunications were based on several different standards over the world, and even at the time major operators negotiate for the third generation licenses, it seems UMTS, CDMA2000 and TD-SCDMA cannot achieve one single standard. A great challenge would be to develop flexible, re-configurable mobile phone handsets that could switch from one standard to another. To do so, MEMS technology is expected as a promising solution to provide tiny, low-consumption tunable components. Moreover, enhancing MEMS technologies to be compatible with IC processing, a novel architecture can be used for a MEMS-based transceiver that could reach the ultimate goal of a fully-integrated single-chip system. Indeed, it has been recently demonstrated that every off-chip, bulky, and expensive passive component present in a typical superheterodyne transceiver front-end could be advantageously replaced by an RF-MEMS counterpart. For example, micro-mechanical resonators could avoid the use of ceramic, SAW, and quartz off-chip resonators to allow low-loss filtering, mixing and carrier generation. But that kind of micro-scale resonators requires high quality factor and temperature stability to achieve highly selective filtering and low phase-noise frequency references. So, to demonstrate this ability, resonators and filters with center frequency up to 300 MHz were designed, and for their fabrication, two processes have been undertaken: an epitaxial thick-film polysilicon industrial technology and a thin-film polysilicon-based technology made compatible with a CMOS-SOI technology.