An indirect current sensing technique for IDDQ and IDDT tests is proposed in this paper. This is accomplished by utilizing the pervasive on-chip voltage regulators and thus have little or no impact on CUT's design and its performance. We demonstrate that the proposed technique can be applied to both IDDQ and IDDT tests. Experiments were successfully conducted in SPICE simulations assuming the TSMC 0.18μm CMOS technology.

IT is with great pleasure that we introduce the special section on Design and Test of Systems-on-Chips (SoC) to the readership of the IEEE Transactions on Computers. This special section consists of eight papers that have been selected to cover a wide spectrum of techniques and applications which are encountered in the design, manufacturing, assembly, and test of today’s SoC. These papers are authored by outstanding researchers and cover experimental and speculative topics. As with all special sections, these topics are only representative of the publically available literature currently provided by the technical community. Systems-on-a-Chip (SoC) represent a rapidly growing and promising field in the electronic and computer industry. Such tremendous growth is the result of significant advances in microelectronic technology that make it possible to build on the same silicon substrate complex systems, including electronic (analog, digital, and mixed mode), mechanical, optical, RF, and microwave cores, as well as sensors, actuators, and software-based systems. As a result, SoCs are very complex hardware/software systems, offering high-performance features. Examples of possible applications include wireless systems, real-time control systems, space exploration systems, and others. SoCs offer the inherent advantages in which computers and their digital domain can be merged to a variety of technologies and applications which, in the past, were attained at boardlevel. The design and test of such complex systems, however, still constitutes a major challenge. From a design point of view, the ability to have a correctly functioning SOC depends on the ability to design and analyze a mixed-technology and to properly account for the interactions among the various cores. Proper management of interfaces between diverse cores and synchronization are examples of the problems to be faced. The unavailability of proper design and simulation tools for such complex systems and the limited resources for different technologies (such as mixed-signal systems) make such an effort rather difficult. The relation between the different modules of an SoC must be properly established using advanced techniques whose technological basis is just emerging. It is expected that these techniques will be highly inter and intradisciplinary in nature, thus involving designers with different backgrounds. Configurability and programmability of the cores in an SoC suggest that wide applicability of these systems is indeed possible with great flexibility in integration. A further issue that designers are confronting is the evaluation of different configurations associated with the high density integration of cores. The merging of different technologies (such as digital and analog) on a single chip is also of high speculative interest because the manufacturing and organization of these systems is in its infancy. These new features must be evaluated at the early design stages because they have a considerable effect on the performance of SoCs as well as their viability for cost-effective implementation. From a testing point of view, the development of proper test access mechanisms is one of the major challenges to be faced in the near future, as indicated also by the 1999 International Technology Roadmap for Semiconductors. The test access mechanisms must be compatible with the IEEE P1500 standard, which was developed for embedded core testing and which leaves the problem of the Test Access Mechanism (TAM) design to the system integrator. Several test access mechanisms have been proposed, including dedicated test bus, multiplexed access, etc., but the goal is to find a solution allowing the best trade-off between the test quality and cost (including the testing time). To evaluate test quality, however, complex failure mechanisms which might occur in such complex systems should also be evaluated. As an example, the possible occurrence of undesired coupling, noise, and skews between clock signals of diverse cores are some of the simplest failures which may affect the operation of the interfaces among the cores. Proper models, fault simulation tools, and test quality figures are needed. Testing time should also be reduced. In fact, while the design and test of SoCs requires a long time (similar to any computer system), the time-to-market of an SoC should be kept as short as possible to meet today’s consumers’ changing requirements. The high performance possibly offered by the integration of complex systems on the same chip makes SoCs very promising for real-time applications, like control systems for automotive, avionic, space, chemical plants, etc. As an example, the first prototypes of SOCs, including electronic and mechanical cores, have already been employed by NASA for space exploration missions. Such a promising application potential, however, poses the problem of reliable design and verification as well as correct design and test. In the past, fault tolerance has been generally adopted to electronic systems for many critical mission applications. The possible adoption of fault tolerance techniques for SoCs (to include not only electronics, digital IEEE TRANSACTIONS ON COMPUTERS, VOL. 55, NO. 2, FEBRUARY 2006 97

In this paper, we presents a programmable jitter generator. Different from the traditional jitter generator that uses the analog phase modulation (PM) technique to generate only non-Gaussian distributed jitter components, the proposed jitter generator uses digital techniques. It consists of a voltage controlled delay chain, jitter control block, and some basic digital components. It can generate not only the non-Gaussian distributed jitter component, but also the Gaussiandistributed jitter component. In addition, almost all jitter characteristics are controllable. This jitter generator can be used in jitter tolerance test and jitter transfer function measurement. A Xilinx XC4010 FPGA chip is used to validate this design.

We present in this paper an on-chip approach to obtain timing characterization for the ever faster high-speed communication systems. In the proposed short time interval measurement circuit, we use a time-to-digital converter, which consists of a charge pump, a comparator with hysteresis, a 6-bit digital counter, and a capacitor. During the measurement, we control a current source and a current sink to charge or discharge a common capacitor, and record the time length ratio of the charging and discharging process. Using this method, we can easily calculate most of the time-domain parameters. Because the measurement process is independent of the absolute value of the capacitor and current amplitude, this method minimizes the impact of the process variations.

We propose a BICS-only method for concurrent error detection (CED) where a built-in current sensor (BICS) is solely responsible for detecting faults and errors. Due to the wide applicability of the BICS, this approach can be applied directly to combinational circuits, sequential circuits, and even some analog circuits. A dependability model was developed to study the effectiveness of the proposed BICS-only method. The unsafe probability of the BICS-only design is sensitive to both fault coverage and testability of the BICS. When used in a duplicated CED system for fault masking, the system reliability is sensitive to the fault coverage, but not to the testability of the BICS. Next, we show that a dramatic increase in unsafe probability is possible if the BICS cannot perform detection at every system clock cycle. A higher testability for BICS will, contrary to our intuition, make the unsafe probability higher. For duplicated CED applications, the reliability will be even lower than that of a nonredundant system. Therefore, the design criteria for BICS in the BICS-only method, in the order of importance, are: operating speed, fault coverage, and testability.

In Fig. 3 of [1], some carry outputs have been labeled with incorrect polarity. Fig. 1 below shows the updated design. The author would like to thank Khalil Habash and Chien-In Henry Chen of Wright State University for bringing this to his attention. © 1998, IEEE

This paper presents a fast binary adder in static CMOS realization. While the carry derivation is similar to that in a conditional-sum adder, the proposed adder is also similar to that of a spanning tree carry lookahead adder in the sense that only selected carry bits are generated and the sum bits are produced by carry-select adders. In a 1.2 /spl mu/m static CMOS realization, the proposed adder adds two 32-bit operands in 3.28 ns. This delay is measured from the assertion of the input to the arrival of the slowest sum bit.

A typical self-checking circuit has an unordered code encoded output. The optimal scheme needs [log(r+1)] check bits, where r is the number of unique weights in all output patterns. A hyper optimal scheme for self-checking output encoding is proposed in this paper where the number of check bits will be further reduced in some cases. Two algorithms are presented to search for the hidden m-out-of-n code words. The hidden m-out-of-n code words are found when all unique output patterns, specified by the circuit specification, in the n selected output bits have exactly m 1s. The output bits that belong to the hidden m-out-of-n code words are then excluded from further encoding. Typically, the number of added check bits of the proposed technique ranges from 0 to [log(p+1)], where p/spl les/r. When hidden m-out-of-n code words exist, applying the proposed scheme usually results in significant hardware cost and delay time reduction. In the five MCNC FSM benchmark circuits that have been identified with hidden m-out-of-n code words, 10% to 41% hardware reductions are exhibited compared to the theoretically optimal separable code encoding scheme. In addition, 7% to 45% reductions in checking delays are demonstrated for the same circuits compared to the separable code encoding scheme.

We propose a probabilistic measure for self-checking (SC) circuits that is analogous to reliability of fault-tolerant systems. This measure is defined as the probability to achieve totally self-checking (TSC) goal at the lth cycle: TSCG(t). TSCG provides insight to the worst case dynamic behavior of SC circuits with respect to the application environment and component failure rates. TSCG surpasses the TSC definitions in determining the applicability of a circuit in a given application environment. An SC circuit achieves TSC goal when no erroneous information or data is propagated beyond the boundary of this circuit. TSCG is therefore the probability that this fault confinement mechanism is intact. The SC properties are obtained through adding hardware redundancy to the original digital design, which means that an SC circuit has a higher failure rate than the original circuit. Further, there are tradeoffs between the level of hardware redundancy, the reliability, and the TSCG. We give several examples to clearly demonstrate these tradeoffs for different design environments. We emphasize that the TSCG is intended to provide a mean of dynamic error handling performance evaluation of SC designs. The TSC definitions and alike are still intact, since a cost-effective SC circuit must begin with a TSC circuit. The TSCG gives confidence in the use of cost-efficient error control codes and/or reduction in error handling capability. Analogous to reliability, the TSCG can be used in product specifications. This is a crucial step toward the practical applications of TSC or CED circuits.

We present a strongly code disjoint (SCD) built-in current sensor (BICS) based on self-exercising concept. The integration of this SCD BICS with a self-checking circuit achieves the totally self-checking goal in static CMOS realizations, even in the presence of stuck-on and bridging faults, and results in a strongly fault-secure realization. Low-cost and high fault coverage is attractive for many high reliability and critical applications.>

Reliable floating-point arithmetic is vital for dependable computing systems. It is also important for future high-density VLSI realizations that are vulnerable to soft-errors. However, the direct checking of floating-point arithmetic is still an open problem. The author presents a set of reliable floating-point arithmetic algorithms for low-cost residue encoded and Berger encoded operands, respectively. Closed form equations are derived for floating-point addition, subtraction, multiplication, and division. Given the standard IEEE floating-point numbers, the proposed reliable floating-point multiplication algorithms for low-cost residue encoded operands are extremely low-cost: it requires less than 8% of hardware redundancy in all cases. For reliable floating-point addition and subtraction, the author finds the hardware redundancy ratios of applying low-cost residue code is about the same as that of applying Berger code: less than 40% of hardware redundancy for single precision numbers and about 16% for double precision numbers. For reliable floating-point division, Berger encoded operands yields hardware cost-effectiveness: about 45% for single precision numbers and about 36% for double precision numbers.>

We analyze the error behavior of content addressable memories and provide necessary and sufficient conditions to protect them. Single error tolerant designs are demonstrated for bit- and byte-organized content addressable memories. This level of protection is equivalent to that of the conventional ECC protection in memory subsystems.>

The authors present closed-form check-predicting equations for deriving Berger checks (J.M. Berger, 1961) for array multipliers and array dividers, respectively. Braun's array multipliers and Guild's array dividers are examined. Example check circuits are also presented.>

Totally self-checking (TSC) Berger code checker designs are presented. The generalized Berger check partitioning is derived. It is proven that a TSC Berger code checker can be constructed from a TSC m-out-of-n checker. For a TSC Berger code checker design, no two-output checker exists for information length 2/sup r-1/, for any positive nonzero r. The presented approach solves this open problem.>

A set of reliable floating-point arithmetic algorithms for Berger encoded operands is presented. Closed-form equations are derived for floating-point addition, subtraction, multiplication and division. Given the IEEE floating-point number standard, the redundancy requirements of the proposed scheme are 39.47% for addition/subtraction, 45.65% for multiplication, and 45.44% for division of single precision numbers. The scheme uses only 16.14% for addition/subtraction, 36.44% for multiplication and 36.02% for division of double-precision numbers.>

CMOS is a popular technology today for very large scale integrated (VLSI) circuits. But, conventional functional testing cannot guarantee the detection of some defects. Built-in current testing has been suggested to enhance the defect coverage. In this paper, the authors present a high-speed built-in current sensing (BICS) circuit design. An experimental CMOS VLSI chip containing BICS is described. The power bus current of an 8*8 parallel multiplier is monitored. This BICS detects all implanted short circuit defects and some open circuit defects at a clock speed of 30 MHz (limited by the test set up). SPICE3 simulations indicate a defect detection time of 2 ns.>

A strongly fault secure (SFS) ALU design based on the Berger check prediction (BCP) technique is presented. The fault and error models of a large class of VLSI ALU designs are discussed. The proposed design is proved to be fault-secure and self-testing with respect to any single fault in the ALU part. The proposed BCP ALU is proved to be SFS with any design of BCP circuit. Consequently, a self-checking processor whose data path is encoded entirely in a Berger code can be achieved. An efficient self-checking processor can then be designed.>

IEEE 802.5 token ring standard has been widely used in integrated service networks. Due to the nature of messages, preferences are usually given to voice packets in most implementations of 802.5 standard. Although such an approach is reasonable, it results in ill network resources utilization and inefficient bandwidth distributions among data and voice stations. The authors present a new protocol based on IEEE 802.5 standard that efficiently distributes the network bandwidth between data and voice stations. The results of simulation show that the new protocol achieves the peak data delay improvement when voice traffic is about half of the full load, and achieve none or little data delay improvement when voice traffic is heavy. In other words, the new protocol exploits a better utilization of network resources.>

The authors present the design of an 11-transistor combinational NMOS 1-out-of-3 code checker. The checker is totally self-checking (TSC) with respect to 36 faults out of a total of 58 faults defined at the NMOS switch and layout geometrical levels, and achieves the TSC goal of a checker for most of the fault sequences. The minimum fault sequences under which the TSC goal is lost are composed of at least three faults. This might be considered as a sufficient level of safety for some implementations.>

A novel approach to designing concurrent-error-detecting arithmetic and logic units using Berger code is presented. Several theorems are developed on Berger check predictions for arithmetic and logical operations. Specifically, the Berger check prediction is proposed for additions and subtractions with unsigned numbers as well as signed numbers. Berger check prediction for 16 logical operations and shift operations, multiplication, and division are given. The proposed scheme may provide a considerable saving in the hardware logic (or chip area) in implementing a self-checking arithmetic logic unit (ALU) and may ultimately make feasible a single-chip self-checking microprocessor or reduced-instruction-set-computer (RISC) design.>