Recently power has become the most important factor in VLSI design. As clock network is the largest design element in terms of power consumption in modern low-power Very Large Scale Integration (VLSI) Designs and IoT applications, several studies have been made in order to reduce the power leaks and unnecessary switching of the clock network. The clock gating, as well as the use of Multibit Flip Flops (MBFFs), are some of the widely used low-power technics.In this paper, we presented a novel approach for power consumption reduction in IoT systems by applying an iterative MBFF insertion. we will make several trials on the use of multi-bit Flip-Flops during each phase of logic Synthesis, Placement, and Optimization. In the first trial, we have measured the impact of MBFF merging on power and circuit performance in several development stages using 2-bits and 4-bits MBFFs. In the second trial, we have combined 2-bits and 4-bits MBFFs and measured the power numbers and circuit’s performance. Finally, we have applied an iterative MBFF merging algorithm and measure the PPA (Power, Performance, and Area) impact versus traditional MBFF implementation.The result of this experiment achieved a better total MBFF merging coverage of 76.6%, a good routability maintenance with less congestion, less wire-length by 3.8% leading to a switching power improvement of around 3.3% with no timing and area degradation.

The Internet of Things (IoT) is a fast-emerging field, primed to become the biggest semiconductor market for the electronics industry. Most IoT circuits are battery powered applications, and the autonomy is an extremely important characteristic to be competitive in this market. Leakage power is the main power component that dictate the IoT devices autonomy and their batteries life cycle. Many design iterations are needed to meet the required leakage target due to the absence of precise power and timing models at early design phases, and the absence of strong leakage optimization approaches at final design stages. In this paper, we will present a post-route sizing-based leakage reduction technique as a solution for the short coming of the current design methodology. This new approach was deployed on 31 industrial designs of different customers, sizes, technologies, and complexities, and has realized an average gain of 9.5% of leakage power, and an average reduction of ~1.3% of total power consumption, with an impartial effect on setup timing and an average improvement of 17.11% of hold timing.