Sparse triangular solve (SpTRSV) is widely used in various domains. Numerous studies have been conducted using CPUs, GPUs, and specific hardware accelerators, where dataflows can be categorized into coarse and fine granularity. Coarse dataflows offer good spatial locality but suffer from low parallelism, while fine dataflows provide high parallelism but disrupt the spatial structure, leading to increased nodes and poor data reuse. This article proposes a novel hardware accelerator for SpTRSV or SpTRSV-like directed acyclic graphs (DAGs). The accelerator implements a medium granularity dataflow through hardware-software codesign and achieves both excellent spatial locality and high parallelism. In addition, a partial sum caching mechanism is introduced to reduce the blocking frequency of processing elements (PEs), and a reordering algorithm of intranode edges’ computation is developed to enhance data reuse. Experimental results on 245 benchmarks with node counts reaching up to 85392 demonstrate that this work achieves average performance improvements of$7.0\times $(up to$27.8\times $) over CPUs and$5.8\times $(up to$98.8\times $) over GPUs. Compared with the state-of-the-art technique (DPU-v2), this work shows a$2.5\times $(up to$5.9\times $) average performance improvement and$1.7\times $(up to$4.1\times $) average energy efficiency enhancement.

A novel integrated single-inductor dual-output buck converter based on the ripple control technique is presented, which can provide two independent output voltages (1.2 and 1.8 V) only using one inductor. The peak current common-mode and ripples compare differential-mode are adopted to improve the system transient response. The converter can automatically switch between pulsewidth modulation and pulse-skip modulation to improve the light load conversion efficiency. The proposed converter has been fabricated in a 0.18 μm 1P6M CMOS process. The experimental results show the transient response time is about 10 μs and the cross-regulation is less than 0.05 mV/mA while the load current suddenly changes 200 mA. In general, the conversion efficiency at light load is above 86% and the peak efficiency at the full load can achieve 93.5%.

The large end face run-out is a kind of shape and position tolerance, and is an important index in deciding the class of the tapered roller. The auto-measuring and sorting equipments for the tapered roller introduced in this article is an intelligent measuring equipment that orientates in pursuing measurement and choosing of every tapered roller on grinding spot. According to professional standard about the tapered roller, the large end face run-out (notated as SDW) must be measured dynamically during revolving on normal V-shape table. In order to eliminate the disturbance caused by electromagnetism interference and machine vibration, this equipment adopts multi-cycle measuring under single sensor, making better use of the regeneration of the sampling signal and based on analysis of the main factors leading to the large end face run-out and signal characteristics. On the other hand, two kinds of signal-characteristics-based data association threshold filtering algorithm and an improved weight arithmetic mean data fusion algorithm are applied on data processing software embedded in it. This equipment has been proved by practical application and has obtained a Chinese patent.