Demo Data from EDBT 2026 / reviewers in the wild / expert
Yasuko Watanabe
dblp:48/8277
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 2010
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 30% Energy-efficient computing · 30% Cloud and datacenter computing · 30% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Cloud and datacenter computing › resource allocation
dynamic resource allocation |
0.1 | 1 | 2010 | WiDGET: Wisconsin decoupled grid execution tiles · ISCA 2010 |
Energy-efficient computing › power management
energy proportional computing |
0.1 | 1 | 2010 | WiDGET: Wisconsin decoupled grid execution tiles · ISCA 2010 |
Processor architecture and microarchitecture
multicore design |
0.1 | 1 | 2010 | WiDGET: Wisconsin decoupled grid execution tiles · ISCA 2010 |
Methods — techniques the papers use, named apart from their topics
simulation · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2010 | WiDGET: Wisconsin decoupled grid execution tilesabstractThe recent paradigm shift to multi-core systems results in high system throughput within a specified power budget. However, future systems still require good single thread performance--no longer the predominant design priority--to mitigate sequential bottlenecks and/or to guarantee service-level agreements. Unfortunately, near saturation in voltage scaling necessitates a long-term alternative to dynamic voltage and frequency scaling. We propose an energy-proportional computing infrastructure, called WiDGET, that decouples thread context management from a sea of simple execution units (EUs). WiDGET's decoupled design provides flexibility to alter resource allocation for a particular power-performance target while turning off unallocated resources. In other words, WiDGET enables dynamic customization of different combinations of small and/or powerful cores on a single chip, consuming power in proportion to the delivered performance. Over all SPEC CPU2006 benchmarks, WiDGET provides average per-thread performance that is 26% better than a Xeon-like processor while using 8% less power. WiDGET can also scale down to a level comparable to an Atom-like processor, turning off resources to reduce average power by 58%. WiDGET achieves high power efficiency (BIPS3/W), exceeding Xeon-like and Atom-like processors by up to 2x and 21x, respectively. Yasuko Watanabe, John D. Davis, David A. Wood 0001 |
ISCA | 1 |