The paper presents a voltage scalable dynamic-cum-body bias (DB+BB) comparator that uses a degeneration capacitor to prevent complete discharge of the pre-amplifier (pAmp) output nodes. An on-chip controlled bias is provided to the body of input-pair transistors that lowers the threshold voltage, and elongates the charge integration time. It augments the pAmp gain, and reduces the input-referred noise (IRN) and the overall delay. The post-layout simulations in 180nm silicon-on-insulator(SOI) technology demonstrate that the proposed DB+BB pAmp achieves 168.4µV IRN while consuming only 55.52fJ energy per comparison. The proposed comparator achieves a figure-of-merit of 5.3nJ·µV2·ns at 100MHz and 1.2V supply.

In this paper, a low-power quadrature LC-oscillator using the current-reuse technique is presented. In the proposed topology, both the core-and-coupling currents are reused to reduce the power consumption. A quadrature LC-oscillator is designed in CMOS 65 nm technology for Bluetooth at 2.45 GHz. The oscillator consumes 2.8 mA of current from a 0.85 V supply voltage. The oscillator's simulated phase noise at 3 MHz offset from the 2.45 GHz center frequency is -130.162 dBc/Hz, resulting in a figure-of-merit (FoM) of 184.4 dB.

The paper presents power supply induced jitter (PSIJ) analysis of a latch based differential CMOS bootstrapped driver, designed for radiation hard particle detection application. The energy efficient driver circuit consists of bootstrap capacitor, boosted node voltages and reduced number of transistors to enhance the gate voltage for better driving efficiency. The closed-form transfer function of the design is derived to analyse the PSIJ. The circuit has been designed in a 180 nm silicon-on-insulator (SOI) technology for its inherent radiation hard by design (RHBD) characteristics with VDDof 0.9 V and input frequency of 40 MHz. The worst case PSIJ of the driver circuit is 1.65 ps with ±10% of supply fluctuations. The mathematical model for the design shows a good matching with the simulation and exhibits 13% of mean percentage error (MPE).

This article presents a discrete-time parametric amplifier (DTPA) as the signal demodulator for chopper amplifier. Unlike the conventional chopper, the DTPA demodulator features noise-efficient gain augmentation while demodulating the chopped signal. The demodulator also enables low-frequency noise cancellation during the inherent track-and-hold (T/H) process of the charge parametrization. The positive feedback loop and the dc servo loop are implemented for applications requiring larger input impedance and dc input offset cancellation using a bandpass transfer function. Design considerations for the DTPA-based demodulator circuit and the merits and demerits of the chopper-DTPA amplifier are discussed as well. The proposed design has been fabricated in a standard 180-nm CMOS technology node. The complete design occupies 0.127 mm2of the die area and consumes 2.4-μW power from a 1.5 V of VDD. The measurement results show that the DTPA demodulator provides 8-dB gain enhancement while improving on the prior art of T/Hbased demodulator and the amplifier achieves input referred noise voltage of 2 μVrmsin 143-Hz bandwidth.

Parallel Prefix adders are arguably the most commonly used arithmetic units. They have been extensively investigated at architecture level, register transfer level (RTL), gate level, circuit level as well as layout level giving rise to a plethora of mathematical formulations, topologies and implementations. This paper contributes significantly to the understanding of these parallel prefix adders in a couple of ways. Firstly, it attempts to describe various such parallel prefix adders in elegant and consistent formulations. Secondly, a new family of parallel prefix adders is proposed at architecture level. The estimates of the area-throughput characteristics for an instance of this family are also presented. While the speeds achieved by this instance match those achieved by the state of the art adders, their area characteristics exhibit upto 26% improvement.

This paper presents the design of a 6-bit scalable hybrid flash SAR (successive approximation register) analog-to-digital converter (ADC). The ADC has a scalable architecture because of the usage of an inverter based comparator. The conversion time is reduced by adopting a 3-bit/cycle approach. A segmented split-capacitor charge redistribution digital-to-analog converter (CDAC) is used to reduce the DAC settling time and the design area. The ADC is implemented in a 28 nm CMOS technology with the scalable VDDfrom 0.5 V to 1 V. The ADC operates from 10 MHz to 1.1 GHz for a VDDof 0.5 V to 1 V respectively. The design shows 47.7 fJ/conv-step and 29.56 fJ/conv-step for VDDof 0.9 V and 0.6 V respectively.

This paper presents the timing error and power supply induced jitter (PSIJ) analyses of an inverter based high-speed comparator, including the design of common-mode body biasing feedback circuitry. Both the main circuit and the supporting circuitry have been designed and implemented in a standard 28 nm CMOS technology with power supply of 0.9 V. The closed-form transfer function of the comparator including biasing circuitry, used in PSIJ analysis, is derived using symbolic admittance method. The mathematical model shows an agreement with the simulation and exhibits 7.4% of mean percentage error (MPE).

This paper presents a chopper stabilized amplifier with a discrete time parametric amplifier (DTPA) based signal demodulator. The DTPA demodulator enables signal amplification while down converting the chopped signal to baseband frequency. The low frequency noise and chopping ripples are cancelled during the track-and-hold process involved in the parametric amplification. The design is implemented in a standard 180 nm CMOS technology and the layout occupies 0.12 mm2of area. The post layout simulation results confirm the gain augmentation of 9 dB from the DTPA demodulator. The proposed amplifier consumes 1.02 μA DC current from a 1.5 V supply. The achieved input noise spectral density of 147 nV/√Hz gives a noise efficiency factor of 5.4 over 400 Hz bandwidth. Furthermore, the design shows satisfactory performance for -20° C to 80° C temperature range and ±10 % of supply voltage variation at various process corner combinations of transistors. The worst case result is found at slow corner for -20° C with 1.35 V supply and the corner shows 47 dB of gain and 425 nV/√Hz of input noise spectral density.

A high speed pseudo differential three stage operational amplifier has been implemented using a feed-forward compensation technique in a standard 0.13 μm CMOS technology. The three stage inverter based op-amp with feed-forward compensation achieves 11 GHz of unity gain bandwidth for a nominal power consumption 18 mW, and exhibits 39 dB of DC gain with phase margin of 62° when driving a differential load of (2×300 fF) at a 1.2 V power supply voltage. At a power supply voltage as low as 0.4 V, the same circuit consumes 0.1 mW and achieves 79 MHz of unity gain bandwidth. The proposed op-amp achieves a figure of merit (FOM) [1] of 440 at 1.2 V, and 190 at 0.4 V.

This work presents a feed-forward technique to reduce the third order harmonic distortion of a parametric amplifier. A prototype design of an nMOS based differential parametric amplifier with supporting circuits were integrated on a standard 0.13 μm CMOS technology. A comparison between a regular parametric amplifier, and a parametric amplifier with feed-forward distortion cancellation, demonstrates a mean reduction of third order harmonic distortion of -13 dB. This comes at a cost of a maximum gain reduction of 0.9 dB.