This paper presents a high-speed chopper amplifier for precise phase current sensing. It is implemented as a fully-differential difference amplifier (FDDA) in a 180 nm Bipolar CMOS DMOS (BCD) technology. Due to the chopping principle, the input referred noise power spectral density is below 10 nV/√Hz. The gain of the amplifier can be precisely adjusted in the range of approximately 50 dB by tuning the chopper frequency. The 3 dB bandwidth ranges from 200 kHz up to 1 MHz depending on the chopper frequency.

Automotive Ethernet is considered to be the backbone of future in-vehicle data communication. One main feature is its ability to simultaneously transmit data and energy via power over data lines (PoDL). This article proposes the design of a single-ended high-voltage (HV)-compliant 11-bit current-steering digital-to-analog converter (DAC). The converter is tailored for the utilization as digitally controlled current source in an adaptive noise-cancellation filter for PoDL networks. Designed in an HV-compliant 180-nm bipolar complementary metal-oxide-semiconductor (BiCMOS) semiconductor technology, the DAC features a monolithically combined topology of two identical 10-bit low-voltage (LV) current-steering DACs supplied at 1.8 V and two complementary HV-compliant output current stages. Main design features of the segmented LV DAC are the utilization of single-ended current cells with an optimized switching logic, proposed to enhance the cells transient performance and energy efficiency. Furthermore, a newly derived$Q^{4}$asymmetric rotated walk switching scheme is investigated. At a maximum output voltage of 60 V, the proposed DAC can deliver a bidirectional output current with the amplitudes of up to 500 mA. The proposed DAC exhibits the highest voltage compliance combined with the highest output current compared with related works. It also features the second highest resolution. Operated at a sample rate of 10 MS/s with a resolution of 11 bit, a spurious-free dynamic range (SFDR) of 57.8 dB could be measured for a synthesized single tone at 100 kHz, as well as a maximum integral nonlinearity (INL) error of 1.61 LSB and a differential nonlinearity (DNL) error of 1.05 LSB.

Real‐time locating systems (RTLSs) suffer from clock synchronization inaccuracy among their distributed reference nodes. Conventional systems require periodic time synchronization and typically necessitate a two‐way ranging (TWR) clock synchronization protocol to eliminate their measurement errors. Particularly, frequency‐modulated continuous‐wave (FMCW) time‐based location systems pose unique design considerations on the TWR that have a significant impact on the quality of their measurements. In this paper, a valid operation design diagram is proposed for the case of an FMCW time‐based TWR synchronization protocol. The proposed diagram represents an intersection area of two boundary curves that indicate the functionality of the system at a given frequency bandwidth, spectral length, and clock synchronization ambiguity. It presents an intuitive illustration of the measurement’s expected accuracy by indicating a larger intersection area for relaxed design conditions and vice versa. Furthermore, the absence of a working condition can easily be detected before proceeding with the actual system development. To demonstrate the feasibility of the proposed diagram, four scenarios with different design constraints were evaluated in a Monte‐Carlo model of a basic TWR system. Moreover, an experimental measurement setup demonstrated the validity of the proposed diagram. Both the simulation and experimental outcomes show that the indicated valid conditions and the distribution of the measurements’ accuracy are in very good agreement.

A dynamic element matching (DEM) decoder with integrated mismatch calibration control for high-speed current-steering digital-to-analog converters (CS-DACs) and CSDAC- based direct digital frequency synthesizers (DDFSs) is studied and presented. The DEM algorithm achieves very good averaging of mismatch-induced errors in the succeeding CS-DAC. It features a minimum element transition rate, therefore opimizing the power dissipation and ensuring minimal glitch energy at the output. Due to the chosen network-based architecture, with only a few modifications of the hardware, the decoder allows the integration of a comprehensive current source mismatch calibration that can be fully operated in the background and even in parallel to the regular DEM operation. A proof-ofconcept hardware implementation of the presented decoder was fabricated in a 22-nm FD-SOI CMOS process and characterized in a high-speed DDFS system with a sampling rate of 5 GHz. Measurements reveal a significant improvement in the spurious free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR) when the calibration and DEM are enabled. Compared to the state-of-the-art (SoA), the presented DDFS achieves one of the best figures of merit.

Synchronization is one of the most challenging aspects of distributed systems in terms of their scalability. Minimal uncertainties can lead to problems or failures regarding data consistency in globally operating data centers or in distributed sensor arrays. Existing approaches to address these challenges are based on hierarchical synchronization concepts which are well understood and have reached technical maturity, but have the disadvantage of having a single point of failure. However, especially for critical infrastructure or backup more resilient solutions are required. Mutual synchronization where oscillators in a network are coupled bidirectionally without a reference have been considered. Due to the flat hierarchy such systems do not have a single point of failure. This work studies how hierarchical synchronization can be combined with architectures implementing mutual synchronization. A network of three mutually coupled 24 GHz oscillators is used to study how injecting a reference signal into one oscillator affects the dynamics. This can be quantified by analyzing in which range of frequencies the network of mutually coupled oscillators can follow the reference frequency. Measurements on a ring and chain network topology forced by an external reference oscillator shown here are in good agreement with the predictions of a nonlinear dynamical model.

In this research article, a concept for a secondary RAdio Direction And Ranging (RADAR) angle of arrival based system with cooperative targets transmitting at 2.4 GHz and using Multiple Signal Classification (MuSiC) to determine the angles of incidence is investigated. In addition to introducing common algorithms and presenting thorough derivations, the system is first examined through simulations. To prove the concept, hardware, firmware, and software are developed. For MuSiC, we propose three novel methods to obtain the correct incident angle from the spectrum, especially in strong multipath environments. These methods work either for a single spectrum or for a combination recorded at multiple times. Together with the estimated angles of incidence, our methods determine measures on the respective likelihoods. Based on this, we additionally propose two algorithms for computing the final position. Our system is characterized in both a simple 20 m × 15 m outdoor and a 17 m × 13 m multipath indoor environment, where we achieve a mean angular error of 3∘ and a mean positioning error of 0.67 m for the former using only four base stations with four antennas each. Our novel approach shows position accuracy improvements of 15% outdoors and 25% indoors compared to classical MuSiC estimation.

In this research paper, a concept for a 225 GHz frequency quadrupler with phase control in local oscillator paths is investigated. By combining a 56.25 GHz phase shifter with a millimeter wave quadrupler, producing a 225GHz signal, a highly performant way of realizing phase control at up to sub-THz frequencies is studied. Locating the phase shifter in the sub 60GHz band both enhances the phase control and overall gain of the system. A phase control range of 330° is measured. With a de power consumption of 105mW, the system achieves a maximum output power of 0.16dBm and a maximum gain of 21dB outperforming the state of the art by 17dB and 25dB respectively. This results in a factor 40 and 2.5 improvement of drain and gain efficiency respectively. Additionally, the root mean square (rms) gain error is reduced to best in class value of 0.04 dB while maintaining a competitive rms phase error of 4.7°.

A 433 MHz wake-up-receiver has been designed and fabricated in 250 nm BiCMOS technology. In a novel approach, an off-chip switched SAW resonator accumulates energy from the radio wave and subsequently emits it as a voltage pulse. This mechanism delivers passive amplification and filtering of the input signal without additional power consumption. The integrated analog frontend evaluates the height of the voltage pulse in the context of on-off keying. The analog frontend circuitry draws 46 µA - 70 µA (meas.) from a 2.5 V supply. With a bitrate of 10 kbps, the energy per bit efficiency amounts to 17.4 nJ/bit without duty cycling. The active chip area measures 370 µm × 210 µm, In this implementation, a passive pulse voltage amplification of up to 24 dB and an input sensitivity of -78 dBm were measured. A detailed analysis of the switched SAW network in a realistic application shows that a passive voltage amplification of 32 dB is attainable. The functionality of the analog frontend has been verified by measurements.

This paper presents a primary impulse-radio ultra-wideband (IR-UWB) radar system for real-time short-range localization, e.g., for smart traffic and automotive applications. The radar system consisting of an integrated radar transceiver (TRx) using 45-nm SOI CMOS technology and an FPGA-based signal processing. The efficient transmitter (Tx), which complies with the regulations for both indoor and outdoor applications, modulates and emits a seventh derivative Gaussian pulse. In the receiver (Rx), echo signals will be amplified and sampled in real-time. The echo pulses are recovered by signal processing hardware on the FPGA, which is also used to perform simple classification tasks like user warning. The radar system is compact, portable, and power efficient. The Tx has a high-energy efficiency of$\mathrm {11~ \text {p} \text {J} /pulse}$. The proposed radar system achieves very high signal-to-noise ratio (SNR) and range precision. It has a maximum detection range of$\mathrm {15~m }$and a range resolution down to$\mathrm {3~ \text {cm}}$. Moreover, a target of interest can be warned with a latency as fast as$\mathrm {16~\mu s }$by using 1-bit real-time sampling.

This work presents synchronization of two bidirectionally delay-coupled phase locked loop (PLL) systems with voltage controlled oscillator frequencies of 24 GHz to validate a non-hierarchical clock distribution approach. For this purpose, a PLL architecture that allows mutual coupling between two such nodes is introduced. An existing phase domain model is extended to include the nonlinear response of the oscillator to the tuning signal. With this extension the frequencies and phase-relations of self-organized synchronized states can be precisely predicted. This is verified by measurements obtained from two synchronized PLLs for different time delays and division factors. The predictions of the model are in good agreement with the measurements. For time delays up to 14 ns it is shown that self-organized synchronization is feasible at microwave frequencies.

In this paper, a nonlinear analysis of cross- coupled super-regenerative oscillators (SROs) is presented. The start-up and decay envelopes of the oscillator output are studied in relation to the input. The SRO start-up time and the maximal achievable quenching frequency are investigated. For phase modulation purposes, the relation between the initial phases of the input and output signals is investigated. In addition, a frequency-domain analysis is performed to ease the characterization of circuit prototypes at frequencies where time-domain measurements are not possible. The analytical results are verified by circuit-level simulations and measurements of a 2.4-GHz SRO. This study provides design guidelines for the design of SROs in cross-coupled architectures and helps in determining the optimal system parameters when targeting both amplitude and phase modulations. To the authors' best knowledge, this is the first study investigating analytically the phase relation between the SRO input and output signals and the nonlinear large-signal behavior of SROs.

Nowadays, there are a variety of different indoor positioning systems employing diverse techniques. On promising approach is Frequency Modulated Continuous Wave- (FMCW) radar, where in addition to several custom approaches, there already exist commercial ICs. Within this work, we are targeting the extension of these systems towards integrating phase measurements with the ultimate goal to improve accuracy. Initially, we present the underlying math for different hardware settings. Subsequently, we focus on our custom FMCW-radar system and analyse the prerequisites for an integration. It becomes clear that already moderate synchronization jitter of 15 μs together with frequency deviations caused by an excellent 20 MHz crystal exhibiting 3 ppm influences operability. We describe our experiments and highlight modifications to establish the principle on the given hardware. Ultimately, this paper contains many lessons learned to simplify the development of similar systems.

This paper presents the design and characterization of a low power 20 Gb/s 1:4 demultiplexer (Demux) in 45-nm SOI CMOS. For the design of the latch, which is used primarily inside the key building blocks of the 1:4 Demux, a power-speed optimized current-scaling methodology is provided. The results of an electromagnetic (EM) 3D field solver, which was used to simulate the high-frequency performance of the most critical data and clock paths inside the Demux, are presented. The designed 1:4 Demux uses a supply voltage of 1 V, dissipates a total of 77 mW of power, and occupies an active area of 0.122mm2. Among the reported inductorless CMOS 20 Gb/s 1:4 Demuxes, the presented Demux achieves the best energy figure of 3.8 pJ/bit.

In differential signaling systems using copper wires common mode signals are the cause of emission of electromagnetic energy. Especially in Automotive Ethernet systems this is a challenging problem. Beside classical passive components like common mode chokes active circuits can help to reduce the emission. This allows inexpensive and resource-conserving unshielded twisted pair cables to be used. This paper shows the approach of using a mixed-signal control loop based on a comparator and a 8 bit DAC for regulating the common mode voltage of an Automotive Ethernet DAC in 28 nm CMOS. An attenuation for interferers with frequencies up to 500 kHz is achieved and reaches up to 15 dB at maximum. The control loop utilizes the successive approximation algorithm commonly used for delay locked loops and DC trimming in mixed-signal circuits. In contrast to known applications the performance and usability at higher frequencies is considered in this paper. Being a nonlinear, time-variant system an analytical design of the control loop is very difficult. Therefore parametrical measurements show the dependency of frequency, amplitude and signal form of an applied common mode interferer source.

Offset compensation (OC) systems are indispensable parts of multi-Gbit/s optical receiver (RX) frontends. Effects of offset are addressed in this paper. The analytical expression for the highest lower-cut-off frequency of the OC with minimum impact on the sensitivity is found. Existing OC solutions are discussed. Then, a novel mixed-signal (MS) architecture is introduced which uses digital filtering of the signal, and current-digital-to-analog converters (IDACs) to compensate the static offset in the limiting amplifier (LA) and transimpedance amplifier (TIA), as well as continuously track and compensate the TIA offset. By using two feedback loops and a continuous tracking the presented solution offers more functionality than other existing MS architectures. Three RX implementations, with RC, switched-capacitor (S-C) and with the MS-OC architectures, in the same 28 nm bulk-CMOS are compared quantitatively with measurements. The presented MS design reaches a lower-cut-off frequency of under 9 kHz, a dynamic range of over 1 mA, 3. 2μA residual input offset-current and it is compensating the RX via two feedback loops. These are achieved using an area of only 1345 μm2, nearly half of RC-filter based architecture. Although the SC implementation needs less area, its residual offset is 8 times higher. Both conventional implementations have a higher high-pass characteristic of about 20 kHz and can compensate only the offset of the TIA. It is concluded, that the presented system offers a higher flexibility and functionality in implementation, as well as a very good compromise between area, precision and performance over the commonly used RC-filter and S-C filter based solutions.

This work presents an integrated low noise amplifier (LNA), based on an ac-coupled 7-stage common-emitter topology. An analysis on the basic transistor configurations is performed, to show the advantages of a common emitter chain for LNA designs. The circuit is intended for ultra-wideband wireless communication systems at 180 GHz (G-band) and offers a measured gain of 19 dB. The bandwidth of over 80 GHz is one of the highest reported. The simulated noise figure is 7.1 dB at 180 GHz and the group delay variation is below 7 ps. The input referred 1-dB compression point occurs above -30 dBm, while the total dc power consumption is 42 mW. The final chip occupies an area of 0.55 mm2and is implemented in a 130 nm SiGe BiCMOS process, which offers a maximum oscillation frequency fmaxof 450 GHz.

With the explosion of the number of compute nodes, the bottleneck of future computing systems lies in the network architecture connecting the nodes. Addressing the bottleneck requires replacing current backplane-based network topologies. We propose to revolutionize computing electronics by realizing embedded optical waveguides for onboard networking and wireless chip-to-chip links at 200-GHz carrier frequency connecting neighboring boards in a rack. The control of novel rate-adaptive optical and mm-wave transceivers needs tight interlinking with the system software for runtime resource management.

This brief presents a 4-bit digitally controlled differential delay element (DCDE) with high-speed and high-resolution capability, two challenging requirements in the design of delay elements. Two input bits, inside the differential current-mode logic (CML) DCDE, regulate its bias current and the resistive load, while the other two bits configure the output capacitive load enabling the presented DCDE to achieve a phase shift of 20 ps and an average resolution of 1.25 ps. Designed in 45-nm silicon-on-insulator (SOI) CMOS, the DCDE dissipates 4 mW of power under maximum biasing condition and can operate up to 10 Gb/s while adding only 0.6 ps of root-mean-square jitter to the delayed input. To the best of authors knowledge, the designed DCDE is the first 4-bit low-jitter 10-Gb/s variable-load CML DCDE offering a time resolution of 1.25 ps, making it a suitable candidate for high-speed and high-resolution applications.

In this paper a modified current switching cell suitable for binary current-steering digital-to-analog converters (DAC) is introduced. An extensive analysis based on the slew rate (SR) and input capacitance calculation is performed, and compared against circuit level simulations. The analysis is focused on the SR-induced bandwidth as it is a limiting factor for high-speed performance of binary DACs. It is shown that the proposed approach provides around 40% lower input capacitance and, consequently, more than 60% higher SR at high-current cells compared to a commonly utilized cascode differential pair. It also shows a closer capacitance ratio between the most significant and least significant bits, leading to closer dynamic response among DAC switches compared to a fully binary realization of DAC cells.

This paper presents a fully-differential frequency doubler integrated in 130 nm SiGe BiCMOS technology. To obtain a differential output signal, the conventional push-push topology is extended. The benefits of this approach are investigated with non-linear circuit analysis and discussed. While both the conventional push-push doubler and the Gilbert-cell doubler only suppress the odd harmonics, the extended topology enables the further suppression of the fourth harmonic. The circuit requires a set of phase-shifted versions of the input signal, which are generated on-chip with a polyphase filter. The proposed approach is validated with measurements of the fabricated circuit: an output power of -4 dBm at the 1 dB compression point with a -3 dB output bandwidth of 10 GHz from 55.6 GHz to 65.6 GHz is reported. With a low power consumption of 23.5 mW, a conversion gain of -15 dB and a fundamental suppression of 42 dB are achieved around the center frequency. A method to improve the conversion gain is discussed in the conclusion.

As the global IP traffic and its demand for computation increase in a rapid and sustained manner, processor, server, and network architectures are also undergoing a considerable evolution. Two of the manifestations of this evolution are the integration of a large number of computing nodes in a single server and the interconnection of many servers via high-speed communication links. At present, however, the node-to-node communication bandwidth is one of the severest resource bottlenecks in massively parallelized applications. There is a concerted effort by the academia and the industry to achieve higher data rate by assembling multiple parallel links. This effort, however, is inherently limited by many constrains, including space. Optical interconnects, on the other hand, promise superior data rates, lower transmission losses, and less inter-channel crosstalk when compared to electrical interconnects. Development in this area promise data rates in the range of Tera bits per second per link and beyond. So far, however, little attention is given to the power adaptiveness of optical interconnects. In this paper, we present an optical interconnect concept which adjusts its power consumption in response to the change in the statistics of the incoming workload. The several components of the link have been designed and developed in hardware. Based on initial power and performance measurements of the components, a link model of our optical interconnect was created. The performance-power consumption characteristics of this model was simulated applying different workload statistics and the potential of the energy savings by the adaptivity have been evaluated. It is revealed that the power consumption of our optical interconnect reduces by up to 40% when its workload was exponentially distributed (signifying underutilisation) compared to a Weibull distribution workload (signifying full capacity workload). This study confirms the high potential for power saving in performance adaptive optical interconnects.

This work presents the design of a dual band frequency modulated continuous wave (FMCW) radar receiver (RX) at the 2.4 and 5.8 GHz industrial, scientific and medical (ISM) bands. The designed low noise amplifier (LNA) has a single ended 50 Ω input stage followed by an active balanced-to-unbalanced (balun) stage. The radio frequency (RF) signal is then down-converted to a low intermediate frequency (IF) by a multi-tanh Gilbert cell mixer whose local oscillator (LO) port is driven by an integrated fractional-N phase locked loop (Frac-N PLL). After down-conversion, the resulting IF signal is low pass filtered and amplified by a baseband variable gain amplifier (VGA). Fabricated on an IBM 0.18 μm BiCMOS process, the measured RX performance is in good agreement with simulations achieving a measured maximum conversion gain (CG) of 82.0 and 77.2 dB and a noise figure (NF) of 7.3 and 8.0 dB at the 2.4 and 5.8 GHz bands respectively. The receiver consumes 22.3 mA from a 3 V supply and occupies a chip area of 0.32 mm2. When used as a primary FMCW radar transceiver (TRX), the designed chip achieves a ranging precision of 0.30 and 0.31 mm at the 2.4 and 5.8 GHz bands respectively. To the best of the author's knowledge, this dual band FMCW radar TRX has the highest level of integration reported in the literature.

This paper describes a new, robust system-architecture for common-cathode (CC) vertical-cavity surface-emitting laser (VCSEL) drivers for highly-scaled CMOS technologies with low supply voltages. The concept implies converting the input signal into a current which is transferred to an amplifier built in a floating well by the level-shifter. Setting the potential of the well as high as the parasitic diode break-down voltage, a high DC bias voltage is possible for the VCSEL, several times higher than the gate-oxide break-down of CMOS technologies. The architecture is demonstrated with the design of a VCSEL driver in 80 nm CMOS with 1.2 V breakdown. The VCSEL DC bias can go as high as 4.5 V. The fabricated chip was bonded to a CC VCSEL. Electrical, optical and robustness measurements were performed. The optical eye was open until 17 Gbps at a bit-error-rate (BER) of 10-12with only 60 mW power consumption including the VCSEL current. The driver met the electrical robustness evaluation offering a more reliable alternative to stacked CC architecture. The active area is of only 0.003 mm2, one of the smallest existing VCSEL diode drivers for this data-rate.