Abstract Hardware trojans are malicious circuits which compromise the functionality and security of an integrated circuit (IC). These circuits are manufactured directly into the silicon and cannot be fixed by security patches like software. The solution would require a costly product recall by replacing the IC and hence, early detection in the design process is essential. Hardware detection at best provides statistically based solutions with many false positives and false negatives. These detection methods require more thorough explainable analysis to filter out false indicators. Existing explainability methods developed for general domains like image classification do not always provide the actionable insights hardware engineers need. A question remains: how do domain-aware property analysis, model-agnostic case-based reasoning, and model-agnostic feature attribution techniques compare for hardware security applications? This work compares three categories of explainability for gate-level hardware trojan detection on the Trust-Hub benchmark dataset: (1) domain-aware property-based analysis of 31 circuit-specific features derived from gate fanin patterns, flip-flop distances, and primary Input/Output (I/O) connectivity; (2) model-agnostic case-based reasoning using k-nearest neighbors for precedent-based explanations; and (3) model-agnostic feature attribution methods (Local Interpretable Model-agnostic Explanations (LIME), SHapley Additive exPlanations (SHAP), gradient) that provide generic importance scores without circuit-level context. The findings show that different explainability approaches offer distinct advantages for hardware security practitioners. The domain-aware property-based method analyzes 31 circuit properties. Detection decisions are explained through familiar concepts like “high fanin complexity near outputs indicates potential trojan triggers.” Case-based reasoning (k-nearest neighbors) achieves 96.51% correspondence between predictions and training exemplars. In contrast, LIME and SHAP show only moderate per-gate agreement (Spearman $$\varvec{\rho = 0.30}$$ mean over $$\varvec{n = 11{,}392}$$ gates, 95% bootstrap CI $$\varvec{[0.29, 0.31]}$$ ; global concatenated $$\varvec{\rho = 0.31}$$ , $$\varvec{p \ll 10}^{\varvec{-300}}$$ ), and yield generic feature importance scores that lack circuit-level context for validation or remediation planning. Detection performance using eXtreme Gradient Boosting (XGBoost) classification with optimized threshold achieves 48.08% precision and 69.44% recall on 11,392 held-out test gates (F1 = 0.568, Matthews Correlation Coefficient (MCC) = 0.575, area under the precision-recall curve (AUPRC) = 0.637) at the optimized threshold of 0.940. This represents a 4.25-fold precision improvement over a support vector machine (SVM) baseline reimplemented under identical experimental conditions (11.33% precision, 70.83% recall, F1 = 0.195 at threshold 0.050) with a 7.4-fold reduction in false-positive density (4.74 vs. 35.0 FP per 1,000 gates). Random Forest achieves comparable F1 (0.555, 58.46% precision, 52.78% recall) with half the false-positive density of XGBoost (2.37 vs. 4.74 FP per 1,000 gates), confirming that the explainable AI (XAI) findings generalize across classifier choices. Additionally, gradient-based feature attribution (Simonyan et al., 2013), with a speedup factor of 7 over SHAP, yields the same model-agnostic feature weights as SHAP and LIME, confirming that computational efficiency alone cannot substitute for domain-aware interpretability. This work provides empirical evidence comparing domain-aware property analysis, model-agnostic case-based reasoning, and model-agnostic feature attribution techniques for hardware security applications. The results show that property-based and case-based approaches offer complementary advantages: domain alignment and precedent-based interpretability, respectively, compared to generic feature rankings. These findings have implications for XAI deployment across domains where practitioners must validate and act on Machine Learning (ML) predictions.

Integrated Circuits (IC) are typically designed based on tradeoffs among performance, power and cost. Designers perceive electromigration as a failure mechanism or as a sign-off rule rather than as an additional tradeoff parameter. This paper describes a design methodology to perform tradeoffs driven by lifetime concerns due to electromigration.

The integration of reusable IP blocks/cores is a common process in system-on-chip design and involves manually comparing/mapping IP specifications against system requirements. The informal nature of specification limits its automatic analysis. Existing techniques fail to utilize the underlying conceptual information embedded in specifications. In this paper, we present a methodology for specification analysis, which involves concept mining of specifications to generate domain ontologies. We employ a semi-supervised expert system with semantic analysis capability to create a collaborative framework for cumulative knowledge acquisition. Our system then uses the generated ontologies to perform component retrieval, drop-in-replacement analysis and design vs. test-plan comparisons. We demonstrate our approach by evaluating several IP specifications.

Semiconductor companies often use 3rd party IPs in order to improve their design productivity. In practice, there are risks involved in using a 3rd party IP as bugs may creep in due to versioning issues, poor documentation, and mismatches between specification and RTL. As a result of this, 3rd party IP specification and RTL must be carefully evaluated. Our methodology addresses this issue, which cross-correlates specification and RTL to discover these discrepancies. The key innovative ideas in our approach are to use prior and trusted experience about designs, which include their specs and RTL code. Also, we have captured this trusted experience into two knowledge bases (KB), Spec-KB and RTL-KB. Finally, knowledge base rules are used to cross-correlate the RTL blocks to the specs. We have tested our approach by analyzing several 3rd party IPs. We have defined metrics for specification coverage and RTL identification coverage to quantify our results.

In a component based engineering approach, a system can be envisioned as an assembly of reusable and independently developed components. In order to produce automated tools to support the selection and assembly of components, precise selection and retrieval strategies based on product specifications are needed. Conventional approaches use keyword based models for automatically retrieving specification documents that match a set of requirements. These approaches typically fail to mine relationships and spotlight excessively on injective matching. In this paper, we propose a Neuro-fuzzy Concept based Inference System (NEFCIS) which is a novel hybrid expert system approach targeted to extract concepts and retrieve relevant information using the excerpted concepts rather than only keywords. By infusing fuzzy logic into our model, we can process the queries with greater precision and produce deeper knowledge inferences. We describe the basic principles of the proposed methodology and illustrate it with example scenarios.

The number of Soft-IP vendors and designsbecoming available on the global market is growing at aphenomenal rate. The current practice of evaluating Soft IPsusing their specification is a time consuming manual process. A specification document is primarily written in English, which serves as a common language for internal product development teams as well as customers. Designers have a preference for writing specifications in an informal natural language using text and notations, including diagrams, charts and tables. The lack of formality of specification documents is a limiting factor intheir analysis. The current state-of-the-art in hardware design lacks any specification analysis technique. In this paper, we present a knowledge-guided methodology for specification analysis that can automatically analyze specification documents. Our approach avoids formal specification. Instead we rely on domain-based ontologies to capture design behavior. We tested our approach by analyzing floating point specification from several third party IP vendors. We define spec coverage and requirement coverage metrics to quantify our results.

Hardware Trojan attack in the form of malicious modification of a design has emerged as a major security threat. Sidechannel analysis has been investigated as an alternative to conventional logic testing to detect the presence of hardware Trojans. However, these techniques suffer from decreased sensitivity toward small Trojans, especially because of the large process variations present in modern nanometer technologies. In this paper, we propose a novel noninvasive, multiple-parameter side-channel analysisbased Trojan detection approach. We use the intrinsic relationship between dynamic current and maximum operating frequency of a circuit to isolate the effect of a Trojan circuit from process noise. We propose a vector generation approach and several design/test techniques to improve the detection sensitivity. Simulation results with two large circuits, a 32-bit integer execution unit (IEU) and a 128-bit advanced encryption standard (AES) cipher, show a detection resolution of 1.12 percent amidst ±20 percent parameter variations. The approach is also validated with experimental results. Finally, the use of a combined side-channel analysis and logic testing approach is shown to provide high overall detection coverage for hardware Trojan circuits of varying types and sizes.

Many industrial systems, sensors and advanced propulsion systems demand electronics capable of functioning at high ambient temperature in the range of 500-600°C. Conventional Si-based electronics fail to work reliably at such high temperature ranges. In this paper we propose, for the first time, a high-temperature reconfigurable computing platform capable of operating at temperature of 500°C or higher. Such a platform is also amenable for reliable operation in high-radiation environment. The hardware reconfigurable platform follows the interleaved architecture of conventional Field Programmable Gate Array (FPGA) and provides the usual benefits of lower design cost and time. However, high-temperature operation is enabled by choice of a special device material, namely silicon carbide (SiC), and a special switch structure, namely Nano-Electro-Mechanical-System (NEMS) switch. While SiC provides excellent mechanical and chemical properties suitable for operation at extreme harsh environment, NEMS switch provides low-voltage operation, ultra-low leakage and radiation hardness. We propose a novel multi-layer NEMS switch structure and efficient design of each building block of FPGA using nanoscale SiC NEMS switches. Using measured switch parameters from a number of SiC NEMS switches we fabricated, we compare the power, performance and area of an all-mechanical FPGA with alternative implementations for several benchmark circuits.

Decimal arithmetic has received considerable attention recently due to its suitability for many financial and commercial applications. In particular, numerous algorithms have been recently proposed for decimal multiplication. A major approach to decimal multiplication shaped by these proposals is based on performing the decimal digit-by-digit multiplication in binary, converting the binary partial product back to decimal, and then adding the decimal partial products as appropriate to form the final product in decimal. With this approach, the efficiency of binary-to-BCD partial product conversion is critical for the efficiency of the overall multiplication process. A recently proposed algorithm for this conversion is based on splitting the binary partial product into two parts (i.e., two groups of bits), and then computing the contributions of the two parts to the partial BCD result in parallel. This paper proposes two new algorithms (Three-Four split and Four-Three split) based on this principle. We present our proposed architectures that implement these algorithms and compare them to existing algorithms. The synthesis results show that the Three-Four split algorithm runs 15%faster and occupies 26.1%less area than the best performing equivalent circuit found in the literature. Furthermore, the Four-Three split algorithm occupies 37.5% less area than the state of the art equivalent circuit.

Hardware Trust is an emerging problem in semiconductor integrated circuit (IC) security due to widespread outsourcing and the stealthy nature of hardware Trojans. Conventional post-manufacturing testing, test generation algorithms and test coverage metrics cannot be readily extended to hardware Trojan detection. As a result there is a need to develop approaches that will ensure trusted in-field operation of ICs, and more generally trust in computing. We present a distributed software scheduling prototype, TADS (Trojan Aware Distributed Scheduling), to achieve a Trojan-activation tolerant trustworthy computing system in a multi-core processor potentially containing hardware Trojans. TADS is designed to be transparent to applications and can run on general purpose multicore PEs without modifications to the operating system or underlying hardware. TADS can, with high confidence, continue to correctly execute its specified queue of job subtasks in the presence of hardware Trojans in the multi-core PEs while learning the individual trustworthiness of the individual PEs. Specially crafted self-checking subtasks called bounty hunters are introduced to accelerate PE trust learning. Also, by learning and maintaining individual PE trustworthiness, the scheduler is able to achieve Trojan containment by scheduling subsequent job subtasks to PEs with high learned trust.

RFID tags will supplant barcodes for product identification in the supply chain. The capability of a tag to be read without a line of sight is its principal benefit, but compromises the privacy of the tag owner. Public key cryptography can restore this privacy. Because of the extreme economic constraints of the application, die area and power consumption for cryptographic functions must be minimized. Elliptic curve processors efficiently provide the cryptographic capability needed for RFID. This paper proposes efficient architectures for elliptic curve processors in GF(2m). One design requires six m-bit registers and six Galois field multiply operations per key bit. The other design requires five m-bit registers and seven Galois field multiply operations per key bit. These processors require a small number of circuit elements and clock cycles while providing protection from simple side-channel attacks. Synthesis results are presented for power, area, and delay in 250, 130 and 90 nm technologies. Compared with prior designs from the literature, the proposed processors require less area and energy. For the B-163 curve, with bit-serial multiplier, the first proposed design synthesized in an IBM low-power 130 nm technology requires an area of 9613 gate equivalents, 163,355 cycles and 4.14 ¿J for an elliptic curve point multiplication. The other proposed design requires 8756 gate equivalents, 190,570 cycles and 4.19 ¿J.

A new SRAM cell model, SRAMT, is presented providing a scalable solution to soft error for various energy levels of protection with minimal power consumption and write time penalties. Our model is based on a classic 6 transistor inner core SRAM cell and an outer core consisting of enhanced tri-state inverters. The outer core will absorb a particle strike at a sensitive node of the SRAM cell without a major impact on write time performance or area overhead. The model provides an on-demand protection due to the fact that the outer core can be shut off during non-essential operating mode. The on-demand aspect of the design provides a much more favorable power consumption overhead compared to the existing hardening technique. The gains in power consumption overhead reduction increase as we scale down the process technology from 90 nm to 32 nm. We simulated extensively our model and provided results for various energy levels of soft error protection. We also compared our method to the standard hardening technique in terms of layout area, performance and power consumption overhead for for 90 nm, 65 nm, 45 nm and 32 nm process technologies.

There have been serious concerns recently about the security of microchips from hardware trojan horse insertion during manufacturing. This issue has been raised recently due to outsourcing of the chip manufacturing processes to reduce cost. This is an important consideration especially in critical applications such as avionics, communications, military, industrial and so on. A trojan is inserted into a main circuit at manufacturing and is mostly inactive unless it is triggered by a rare value or time event; then it produces a payload error in the circuit, potentially catastrophic. Because of its nature, a trojan may not be easily detected by functional or ATPG testing. The problem of trojan detection has been addressed only recently in very few works. Our work analyzes and formulates the trojan detection problem based on a frequency analysis under rare trigger values and provides procedures to generate input trigger vectors and trojan test vectors to detect trojan effects. We also provide experimental results.

There have been many solutions to create a soft error immune SRAM cell. These solutions can be broken down into three categories: a) hardening, b) recovery, c) protection. Hardening techniques insert circuitry in an SRAM cell possibly duplicating the number of transistors. Recovery techniques insert current monitors in SRAMs to detect SEUs and they employ error correcting codes or redundancy to mitigate these effects. These techniques do not scale very well. Protection methods use capacitors in SRAM cells to absorb the excessive charge. Although they provide sufficient protection, they affect adversely the write time.

In this paper we present an efficient design technique for implementing the elliptic curve cryptographic (ECC) scheme in FPGAs. Our technique is based on a novel and efficient implementation of modular multiplication which is the core operation of ECC. To implement large bit-length multiplications we used a novel partitioning and pipeline folding scheme to fit at least 256-bit modular multiplications on a single Virtex-4 FPGA. Comparisons to several other schemes are presented.

In this paper, we present an analysis methodology to compute circuit node sensitivity due to charged particle induced delay (timing) errors, soft delay errors (SDE). We define node sensitivity metric and describe a step by step procedure to compute node sensitivity. We use mixed-mode simulations to extract accurate current pulses for the characterization of SDE. A technique for logic cell library characterization for SDE is described. Our approach is orders of magnitude faster than using Spice based analysis and its accuracy is close to Spice. Using our approach, we provide distribution of nodes sensitivity for various ISCAS85 circuits and two adders. Such analysis is important to employ node hardening techniques on selected nodes to increase the reliability of CMOS circuits. We use two test circuits to apply a node hardening technique on the highly sensitive nodes which were determined by our approach. Results are provided for the reduction of the circuit sensitivity

A dynamic coarse-grained reconfigurable architecture which targets computationally intensive applications like multimedia and wireless applications is presented. Fundamental features of the architecture are an interconnection matrix, switch buffers, functional units, and a controller. Important aspects of the architecture is dynamic datapath reconfiguration over each control step of the application. Simulations of several classes of applications with results are also presented. Results of Xilinx Virtex 4 Implementations are provided

High secure cryptographic systems require large bit-length encryption keys which presents a challenge to their efficient hardware implementation especially in embedded devices. Modular multiplication is the core operation in well known cryptosystems like RSA and elliptic curve (ECC). Therefore, it is important to employ efficient modular multiplications techniques to improve the overall performance of the cryptographic system. We present a modular multiplier based on the ordinary Montgomery's multiplication algorithm and a new array multiplication scheme to perform the multiplication. The new modular multiplier is scalable and can be used for large bit-lengths. We also implement the modular multiplier into the Virtex4 FPGA devices and we show that our technique has better performance when compared with other schemes. To implement large bit-length multiplications we used a novel partitioning and pipeline folding scheme to fit at least 512-bit modular multiplications on a single FPGA.

We propose a new built-in current sensor (BICS) to detect single event upsets (SEUs) in SRAM. The BICS is designed and validated for 100 nm process technology. The BICS reliability analysis is provided for process, voltage and temperature variations, and power supply noise. The BICS detects various shapes of current pulses generated due to particle strike. The BICS power consumption and area overhead are also provided. The BICS is found to be very reliable for process, voltage and temperature variations and under stringent noise conditions.

In this paper, we introduce an approach for computing soft error susceptibility of nodes in large CMOS circuits at the transistor level. The node sensitivity depends on the electrical, logic, and timing masking. An efficient technique is developed to compute the electrical masking of nodes using characterization tables and inverse pulse propagation. We generated these tables for every logic cell of the library using Spice simulations for a 100 nm process technology. An additional technique to compute the logic masking of the transistor nodes using an automatic test pattern generation tool is described. Our results show that our approach has Spice like accuracy but it is several orders of magnitude faster than Spice. This approach can be used to analyze the vulnerability of circuits to single event upsets at the chip level. Results are provided for ISCAS85 benchmark circuits

This paper describes a self test program design technique for embedded DSP cores. The method requires minimal knowledge of the core's internals and minimal insertion of external LFSR hardware, without scan insertions. The test program consists of a small set of instructions which operate iteratively on pseudorandom data generated by the LFSRs to fully test the DSP core components. The method uses instruction-based test metrics and a program template as a blueprint to generate the test program. The self test scheme has been successfully applied on an industrial-strength DSP core and the results compare favorably to other methods using ATPG and pseudorandom BIST.

We present a new decompression architecture suitable for embedded cores in SoCs which focuses on improving the download time by avoiding higher internal-to-ATE clock ratios and by exploiting hardware parallelism. The bounded Huffman compression facilitates decompression hardware tradeoffs. Our technique is scalable in that the downloadable RAM-based decode table and accommodates for different SoC cores with different characteristics such as the number of scan chains and test set data distributions.

Single event upsets (SEUs) are due to high energetic particle strike at sensitive nodes of CMOS combinational circuits. In this paper, we introduce a type of soft errors which manifests as soft delay. The soft delay is temporary delay in CMOS combinational circuits due to high energetic particle strike. We describe soft delay model which enables us to examine delay in CMOS combinational circuits due to particle strike. As technology scales down, the delay due to particle strike increases, and other factors such as V/sub dd/ scaling, fanout and transistor strength also contribute to increase the soft delay in CMOS combinational circuits.

In this paper we present a new test data compression technique and an associated decompression scheme for testing VLSI chips. Our method is based on our novel use of the much utilized, in software, LZW, particularly LZ77 algorithm. We adapt LZ77 to accommodate bit strings rather than character sets. Moreover, we exploit the large presence of don't cares in the uncompressed test sets that we generated using commercial ATPG tools. Our decompression scheme makes effective use of the on chip boundary scan during decompression and then feeding the internal multiple scan chains for testing. The hardware overhead cost for this scheme is minimal. Experimental results are provided.

A new approach to software reliability estimation is presented that combines operational testing with stratified sampling in order to reduce the number of program executions that must be checked manually for conformance to requirements. Automatic cluster analysis is applied to execution profiles in order to stratify captured operational executions. Experimental results are reported that suggest this approach can significantly reduce the cost of estimating reliability.