Demo Data from EDBT 2026 / reviewers in the wild / expert
Ivan Celanovic
dblp:49/10948
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 2013
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1Applied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Embedded and real-time systems · 50% Integrated circuit design · 25% Processor architecture and microarchitecture · 25% | |
| Interdisciplinary, comprehensive, and emerging computing
1 paper |
Energy systems and smart grids · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Embedded and real-time systems
cyber-physical system platforms |
0.1 | 1 | 2011 | Time-Predictable Computer Architecture for Cyber-Physical Systems: Digital Emulation of Power Electronics Systems · RTSS 2011 |
Processor architecture and microarchitecture › multicore design
heterogeneous multicore |
0.1 | 1 | 2011 | Time-Predictable Computer Architecture for Cyber-Physical Systems: Digital Emulation of Power Electronics Systems · RTSS 2011 |
Integrated circuit design
power electronics |
0.1 | 1 | 2011 | Time-Predictable Computer Architecture for Cyber-Physical Systems: Digital Emulation of Power Electronics Systems · RTSS 2011 |
Embedded and real-time systems
real-time emulation |
0.1 | 1 | 2011 | Time-Predictable Computer Architecture for Cyber-Physical Systems: Digital Emulation of Power Electronics Systems · RTSS 2011 |
Energy systems and smart grids
power electronics |
0.0 | 1 | 2011 | Time-Predictable Computer Architecture for Cyber-Physical Systems: Digital Emulation of Power Electronics Systems · RTSS 2011 |
Methods — techniques the papers use, named apart from their topics
hardware emulation · 0.2circuit compilation · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2013 | MARTHA: architecture for control and emulation of power electronics and smart grid systemsabstractThis paper presents a novel Multicore Architecture for Real-Time Hybrid Applications (MARTHA) with time-predictable execution, low computational latency, and high performance that meets the requirements for control, emulation and estimation of next-generation power electronics and smart grid systems. Generic general-purpose architectures running real-time operating systems (RTOS) or quality of service (QoS) schedulers have not been able to meet the hard real-time constraints required by these applications. We present a framework based on switched hybrid automata for modeling power electronics applications. Our approach allows a large class of power electronics circuits to be expressed as switched hybrid models which can be executed on a single hardware platform. Michel A. Kinsy, Ivan Celanovic, Omer Khan, Srini Devadas |
DATE | 2 |
| 2011 | Time-Predictable Computer Architecture for Cyber-Physical Systems: Digital Emulation of Power Electronics SystemsabstractThe smart grid concept is a good example of a complex cyber-physical system (CPS) that exhibits intricate interplay between control, sensing, and communication infrastructure on one side, and power processing and actuation on the other side. The more extensive use of computation, sensing, and communication, tightly coupled with power processing, calls for a fundamental reassessment of some of the prevailing paradigms in the real-time control and communication abstractions. Today these abstractions are mostly thought of as embedded systems, and the overall framework needs to be reformed in order to fully realize the potential of the emerging field of cyber-physical systems. This paper details the design and application of a new ultrahigh speed real-time emulation platform for Hardware-in-the-Loop (HiL) testing and design of high-power power electronics systems. Our real-time hardware emulation for HiL systems is based on a reconfigurable, heterogeneous, multicore processor architecture that emulates power electronics, and includes a circuit compiler that translates graphic system models into processor executable machine code. We present the hardware architecture, and describe the process of power electronic circuit compilation. This approach yields real-time execution on the order of 1μs simulation time step (including input/output latency) for a broad class of power electronics converters. To the best of our knowledge, no current academic or industrial HiL system has such a fast emulation response time. We present HiL experimental results for three representative systems: a variable speed induction motor drive, a utility grid connected photovoltaic converter system, and a hybrid electric vehicle motor drive. Michel A. Kinsy, Omer Khan, Ivan Celanovic, Dusan Majstorovic, Nikola L. Celanovic, Srini Devadas |
RTSS | 3 |