Demo Data from EDBT 2026 / reviewers in the wild / expert
Giuseppe Fantauzzi
dblp:49/1221
· DBLP profile ↗
3ranked-venue papers
3as first author
0since 2021 · last 1974
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 3 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Electronic design automation · 92% Integrated circuit design · 8% |
Topics — the 9 heaviest of 9, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
logic synthesis |
0.0 | 2 | 1974 | An Algebraic Model for the Analysis of Logical Circuits · IEEE Trans. Computers 1974 NORNAND Maitra Cascades · IEEE Trans. Computers 1968 |
Electronic design automation › hardware verification and test
fault detection |
0.0 | 1 | 1974 | Multiple-Fault Detection and Location in Fan-Out Free Combinational Circuits · IEEE Trans. Computers 1974 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 1974 | Multiple-Fault Detection and Location in Fan-Out Free Combinational Circuits · IEEE Trans. Computers 1974 |
Electronic design automation › circuit analysis
logic circuit analysis |
0.0 | 1 | 1974 | An Algebraic Model for the Analysis of Logical Circuits · IEEE Trans. Computers 1974 |
Electronic design automation › hardware verification and test › fault testing
stuck-at fault testing |
0.0 | 1 | 1974 | Multiple-Fault Detection and Location in Fan-Out Free Combinational Circuits · IEEE Trans. Computers 1974 |
Electronic design automation › logic synthesis › structural synthesis
cascade synthesis |
0.0 | 1 | 1968 | NORNAND Maitra Cascades · IEEE Trans. Computers 1968 |
Integrated circuit design
digital circuit design |
0.0 | 2 | 1974 | An Algebraic Model for the Analysis of Logical Circuits · IEEE Trans. Computers 1974 NORNAND Maitra Cascades · IEEE Trans. Computers 1968 |
Electronic design automation › hardware test
fault localization |
0.0 | 1 | 1974 | Multiple-Fault Detection and Location in Fan-Out Free Combinational Circuits · IEEE Trans. Computers 1974 |
Integrated circuit design › digital circuit design › logic design
logic circuits |
0.0 | 1 | 1968 | NORNAND Maitra Cascades · IEEE Trans. Computers 1968 |
Methods — techniques the papers use, named apart from their topics
indistinguishability class analysis · 0.0algebraic modeling · 0.0function synthesis tests · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1974 | An Algebraic Model for the Analysis of Logical CircuitsabstractThe purpose of this paper is to propose an algebraic model of logical circuits which has been designed to build up efficient analysis and simulation procedures. Giuseppe Fantauzzi |
IEEE Trans. Computers | 1 |
| 1974 | Multiple-Fault Detection and Location in Fan-Out Free Combinational CircuitsabstractTwo algorithms are presented for the detection and location of single or multiple stuck faults in a fan-out free combinational circuit. The algorithms are based on a canonic representation of the indistinguishability classes of faults. The number of tests required in these algorithms are shown to be a linear function of the number of gates in the circuit. Giuseppe Fantauzzi, Alberto Marsella |
IEEE Trans. Computers | 1 |
| 1968 | NORNAND Maitra CascadesabstractAbstract—Maitra cascades are introduced here using two-input NAND and/or NOR. Tests for function synthesis by these kinds of cascades are introduced. The same methods can be used to design a cascade to realize a given function, when it exists. Finally, some procedutes are given for making such a cascade as short as possible. Giuseppe Fantauzzi |
IEEE Trans. Computers | 1 |