Demo Data from EDBT 2026 / reviewers in the wild / expert
Miao Yu 0009
dblp:49/1749-9
· DBLP profile ↗
3ranked-venue papers
2as first author
3since 2021 · last 2025
0009-0004-7730-3437ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-author · 3 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Hardware accelerators and domain-specific architectures · 69% GPUs and heterogeneous computing · 25% Memory systems · 6% | |
| Artificial intelligence
1 paper |
Efficient and distributed learning · 100% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Machine learning › Efficient and distributed learning
parameter-efficient fine-tuning |
0.9 | 1 | 2025 | SSFT: Algorithm and Hardware Co-design for Structured Sparse Fine-Tuning of Large Language Models · DAC 2025 |
GPUs and heterogeneous computing
GPU architecture |
0.9 | 1 | 2025 | The Sparsity-Aware LazyGPU Architecture · ISCA 2025 |
Hardware accelerators and domain-specific architectures
machine learning accelerator |
0.9 | 1 | 2025 | SSFT: Algorithm and Hardware Co-design for Structured Sparse Fine-Tuning of Large Language Models · DAC 2025 |
Hardware accelerators and domain-specific architectures › sparsity exploitation
sparsity-aware accelerator |
0.9 | 1 | 2025 | The Sparsity-Aware LazyGPU Architecture · ISCA 2025 |
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator |
0.7 | 1 | 2023 | Multiply-and-Fire: An Event-Driven Sparse Neural Network Accelerator · ACM Trans. Archit. Code Optim. 2023 |
Hardware accelerators and domain-specific architectures › machine learning accelerator › neural network accelerator
sparse neural network acceleration |
0.7 | 1 | 2023 | Multiply-and-Fire: An Event-Driven Sparse Neural Network Accelerator · ACM Trans. Archit. Code Optim. 2023 |
GPUs and heterogeneous computing
GPU computing |
0.3 | 1 | 2025 | SSFT: Algorithm and Hardware Co-design for Structured Sparse Fine-Tuning of Large Language Models · DAC 2025 |
Memory systems
memory access optimization |
0.3 | 1 | 2025 | The Sparsity-Aware LazyGPU Architecture · ISCA 2025 |
Methods — techniques the papers use, named apart from their topics
structured sparsity · 1.7sparsity-aware PE design · 1.7structured pruning · 0.7activation sparsity exploitation · 0.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | SSFT: Algorithm and Hardware Co-design for Structured Sparse Fine-Tuning of Large Language ModelsabstractA significant number of users depend on Large Language Models (LLMs) for downstream tasks, but training LLMs from scratch remains prohibitively expensive. Sparse finetuning (SFT) has emerged as an effective strategy to reduce both the time and memory requirements of fine-tuning LLMs, achieving accuracy on par with fully fine-tuned models. Although SFT has the potential to achieve superior performance by minimizing computational requirements, SFT on GPUs often underperforms compared to dense algorithms like LoRA due to sparse data accesses that modern GPUs cannot efficiently handle. To address these issues, we propose Structured Sparse FineTuning (SSFT). It comprises a novel algorithm, SSFT-Alg, which introduces predictable sparsity patterns to reduce memory access overhead and enhance regularity in the SFT process. To support SSFT-Alg, an accelerator, SSFT-Hw, is proposed to optimize SSFT-Alg through an innovative sparsity-aware design, avoiding the overhead of sparsity operations on GPUs and optimizing latency and energy efficiency. Experiments with relevant models and benchmarks demonstrate that SSFT achieves comparable accuracy to state-of-the-art models on BERT, LLaMA 2 7B, and LLaMA 2 13B. Moreover, SSFT-Hw outperforms both GPUs and the state-of-the-art sparsity-aware transformer accelerators in throughput by $51.0 \times$ and $1.32 \times$, respectively, while improving energy efficiency by $19.0 \times$ and $1.48 \times$. Miao Yu 0009, Trevor E. Carlson |
DAC | 1 |
| 2025 | The Sparsity-Aware LazyGPU Architecture
Changxi Liu, Miao Yu 0009, Yifan Sun 0002, Trevor E. Carlson |
ISCA | 2 |
| 2023 | Multiply-and-Fire: An Event-Driven Sparse Neural Network AcceleratorabstractDeep neural network inference has become a vital workload for many systems from edge-based computing to data centers. To reduce the performance and power requirements for deep neural networks (DNNs) running on these systems, pruning is commonly used as a way to maintain most of the accuracy of the system while significantly reducing the workload requirements. Unfortunately, accelerators designed for unstructured pruning typically employ expensive methods to either determine non-zero activation-weight pairings or reorder computation. These methods require additional storage and memory accesses compared to the more regular data access patterns seen in structurally pruned models. However, even existing works that focus on the more regular access patterns seen in structured pruning continue to suffer from inefficient designs, which either ignore or expensively handle activation sparsity leading to low performance. To address these inefficiencies, we leverage structured pruning and propose the multiply-and-fire (MnF) technique, which aims to solve these problems in three ways: (a) the use of a novel event-driven dataflow that naturally exploits activation sparsity without complex, high-overhead logic; (b) an optimized dataflow takes an activation-centric approach, which aims to maximize the reuse of activation data in computation and ensures the data are only fetched once from off-chip global and on-chip local memory; and (c) based on the proposed event-driven dataflow, we develop an energy-efficient, high-performance sparsity-aware DNN accelerator. Our results show that our MnF accelerator achieves a significant improvement across a number of modern benchmarks and presents a new direction to enable highly efficient AI inference for both CNN and MLP workloads. Overall, this work achieves a geometric mean of 11.2× higher energy efficiency and 1.41× speedup compared to a state-of-the-art sparsity-aware accelerator. Miao Yu 0009, Tingting Xiang, Venkata Pavan Kumar Miriyala, Trevor E. Carlson |
ACM Trans. Archit. Code Optim. | 1 |