Optical wireless power transfer (OWPT) has emerged as a promising technology for efficient wireless power transfer (WPT), offering advantages, such as directionality, suitability for far-field applications, and the ability to transfer power and data simultaneously. This comprehensive review classifies OWPT systems into laser power transfer (LPT) and light-emitting diodes (LED)-based OWPT. LPT uses the narrow divergence of laser beams for high-density, long-distance energy transfer, making it suitable for applications, such as satellites, autonomous drones, and electric vehicle charging. In contrast, LED-based OWPT offers a safer, more cost-effective solution for low-power applications, especially in the Internet of Things (IoT) domain. It offers advantages, such as lower power consumption and fewer safety restrictions compared to LPT. Innovations in LPT, such as high-intensity laser power beaming, distributed laser charging (DLC), adaptive DLC, simultaneous lightwave information and power transfer, and resonant beam charging are discussed. Also, recent advancements in LED-OWPT, including single-lens and double-lens systems, collimation techniques, and multi-LED arrays, are explored for their potential in powering IoT devices, wearable electronics, and smart infrastructure. First, we present a radar chart comparing various WPT techniques with respect to performance criteria. After reviewing the methods of LPT and LED-OWPT in detail, a comparison of these techniques is provided, evaluating their strengths, limitations, and application suitability. A concluding radar chart offers insights for optimizing OWPT systems tailored to specific applications. Future research directions are identified, emphasizing the need for further advancements in beam alignment, safety protocols, and hybrid systems to enhance OWPT’s scalability and practicality in real-world scenarios.

This paper introduces a fast artifact recovery algorithm (FARA) that uses electrochemical impedance spectroscopy to model the electrode-tissue interface and design an optimum stimulation waveform to minimize the residual artifact duration in single-cell resolution neural interfaces. Results in saline solution with a custom PCB and a 30 $\mu \mathrm{m}$ diameter microelectrode array show a worst case artifact recovery time of 160 $\mu \mathrm{s}$ when measured from the end of the working phase (anodic 500 $\mathrm{n}\mathrm{A}, 250\mu \mathrm{s})$. On average, the proposed algorithm provides an 81% improvement over a triphasic charge-balanced stimulation waveform.

This paper presents the design and measurement of an RF energy harvesting and power management unit that operates across a wide range of available input power, from -24 to +15dBm. The system comprises an adaptive impedance matching network, a single-stage cross-coupled differential-drive rectifier, a start-up charge pump, an adaptive buck-boost converter, a maximum power point tracking (MPPT) circuit and a control loop to regulate the load voltage. The MPPT circuit controls the switching frequency of the buck-boost converter and configures the impedance matching network, optimizing the interfaces between the rectifier and antenna and between the rectifier and the storage capacitor, guaranteeing that the power is being harvested at maximum efficiency. To boost the rectifier output, to accumulate energy in the storage capacitor and to provide energy to the load, a single-inductor buck-boost converter that has two inputs and three outputs is used. Circuit techniques that reduce the power consumption of the control circuits and that allow for adapting the interfaces between the antenna, the rectifier and the load are presented. The peak harvesting efficiency of the system is 40.2%, when presented with an RF source of -9.1dBm available power and 403.5MHz frequency.

This paper presents the design of an ultra-low energy, rakeness-based compressed sensing (CS) system that utilizes time-mode (TM) signal processing (TMSP). To realize TM CS operation, the presented implementation makes use of monostable multivibrator based analog-to-time converters, fixed-width pulse generators, basic digital gates and an asynchronous time-to-digital converter. The TM CS system was designed in a standard 0.18 μm IC process and operates from a supply voltage of 0.6V. The system is designed to accommodate data from 128 individual sensors and outputs 9-bit digital words with an average reconstruction SNR of 35.31 dB, a compression ratio of 3.2, with an energy dissipation per channel per measurement vector of 0.621 pJ at a rate of 2.23 k measurement vectors per second.

Atrial electrogram (AEG) acquired with a high spatio-temporal resolution is a promising approach for early detection of atrial fibrillation. Due to the high data rate, transmission of AEG signals requires considerable energy, making its adoption a challenge for low-power wireless devices. In this paper, we investigate the feasibility of using compressed sensing (CS) for the acquisition of AEGs while reducing redundant data without losing information. We apply two CS approaches, standard CS and rakeness-based CS (rak-CS) on real medical recordings. We find that the AEGs are compressible in time, and, more interestingly, in the spatial domain. The performance of rak-CS is better than standard CS, especially at higher compression ratios (CR), both during sinus rhythm (SR) and atrial fibrillation (AF). More specifically, the difference in the achieved average reconstruction signal-to-noise (ARSNR) in rak-CS and standard CS, for CR = 4.26, in the time domain is 7.7 dB and 2.6 dB for AF and SR, respectively. Multi-channel data is modeled as a multiple-measurement-vector problem and a suitable mixed norm is used to exploit the group structure of the signals in the spatial domain to obtain improved reconstruction performance over l1norm minimization. Using the mixed-norm recovery approach, for CR = 4.26, the difference in achieved ARSNR performance between rak-CS and standard CS is 5 dB and 2 dB for AF and SR, respectively.

Stochastic resonance (SR) is a phenomenon in which noise can be employed to increase the performance of a system. It can e.g. be used to improve the performance of comparator-based circuits. This paper presents the analytical derivation of input-output relation, harmonic distortion, and noise behaviour of a 1-bit ADC using SR. Furthermore, the design of a new signal multiplier based on SR-ADCs is presented. The predicted behaviours are demonstrated by means of simulations. The work presented in this paper shows the potential for analog to digital conversion and integrated signal processing fully based on stochastic resonance.

In this paper we present the design and simulation results of an RF energy harvesting circuit that operates across a wide range of available input power, from -27 dBm to 6 dBm. The system comprises an adaptive impedance matching network, a single-stage cross-connected differential rectifier, a start-up charge pump, an adaptive buck-boost converter and a Maximum Power Point Tracking (MPPT) circuit. The MPPT circuit controls the switching frequency of the buck-boost converter and configures the impedance matching network, optimizing the interfaces between the rectifier and antenna and between the rectifier and the storage capacitor, thereby guaranteeing that maximum power is being harvested. The system is designed in a standard 0.18 pm CMOS technology. The peak efficiency is 49.1% at an available input power of -18 dBm and signal frequency of 403.5 MHz.

In this paper, a power-efficient multiphase Recursive Switched Capacitor (RSC) converter is presented. Conventionally, RSC converters are used to obtain many different output voltages from a fixed input voltage. Here, the converter provides a fixed output voltage of 1 V at 1 mA from an input voltage ranging from 1.4 V to 4.5 V. It has one programmable stage (2:1 or 3:2) followed by four 2:1 stages. Contrary to most conventional topologies, depending on the input voltage, not all the stages are always deployed. This allows to increase the power efficiency of the whole architecture. The flying capacitance of the non-activated stages is transferred to the activated ones. Hence, for any given input voltage, 100% of the on-chip capacitance is always used for the conversion. For a general 2:1 topology, an analytical analysis of the power losses is carried out and the impact of the overdrive voltage of the switches on the power efficiency is quantified. A novel gate-driver technique for the switches involved in the conversion is proposed. It ensures an optimal overdrive voltage of the transistor, irrespective of its source and drain potentials. The 16-phase interleaved converter employs a charge recycling technique and uses a total on-chip capacitance of 3 nF. The RSC converter is designed to be implemented in a standard 40 nm CMOS process which offers a capacitor density of approximately 2nF/mm2. Circuit simulations over the whole input voltage range show a power efficiency never lower than 54% with a peak value of 92.7%.

Achieving an accurate sub-Hz high-pass (HP) cutoff frequency and simultaneously a high accuracy of the transfer function is a challenge in the implementation of analog-to-digital converters for biomedical ExG signals. A structured electronic design approach based on state-space forms is proposed to develop HPΣΔ modulators targeting high accuracy of the HP cutoff frequency and good linearity. Intermediate transfer functions are mathematically evaluated to compare the proposed HPΣΔ topologies with respect to dynamic range. Finally, to illustrate the design method, an orthonormal HPΣΔ modulator is designed to be implemented in 0.18 μm technology which achieves a linearity of 12-bits.

This work proposes a system design for neural stimulators. It eliminates the need for a DC-DC converter which is normally used to increase the battery voltage. Instead it combines the DC-DC converter and stimulator output stage into a single system block. The number of external components needed for the system is reduced to a single inductor only. The system offers high power efficiency operation (theoretical power efficiency of 100% and a simulated efficiency of around 60% over the full output range) by employing switched-mode operation. Furthermore the output has a current source character, making charge balanced stimulation relatively easy to implement. Finally it is also possible to stimulate multiple channels independently with this system. An example design is presented that can stimulate two channels with a maximum output voltage of 10 V, while being powered from a 3.5V battery.

In order to dramatically reduce the size of energy harvesting sensor nodes, it's necessary for a receiver to share the same antenna with an energy harvester. However, the standard 50Ω power matched interface is only designed for the connection of the antenna and the LNA, rather than taking into account the presence of the energy harvester. This paper presents an optimally mismatched antenna interface and an LNA based on this interface for the combination of the energy harvester and the LNA. The interface offers large passive voltage boosting to improve the voltage gain and NF of the LNA in a low power environment, and increases the sensitivity of the energy harvester as well. The interface and LNA have been designed and verified with simulations in AMS 0.18μm technology. A comparison with another LNA design based on a standard 50Ω power matched interface shows the proposed LNA has 12.3dB higher voltage gain and 1.8dB lower NF at a power consumption of 50μW.

Integrating time constants of the order of a few seconds is one of the main bottlenecks in the design of biomedical chips. To achieve a low cut-off frequency with 60 dB linearity, mixed-signal feedback utilizing the properties of a ΣΔ ADC is proposed. To verify the performance, a 10-bit ΣΔ modulator with the proposed technique is designed to be implemented in 0.18 μm CMOS AMS technology. The design is verified by means of simulations in Cadence using RF spectre.

A novel continuous-time level-crossing analog-to-digital converter (LC-ADC) for biomedical application is proposed. Lower power consumption and less design complexity with respect to the conventional designs are achieved due to 1) replacing the n-bit digital-to-analog converter (DAC) with a 1-bit DAC; 2) introducing a 3-input comparator and switching off the idle branches in the following stages when possible; 3) utilizing the opposite polarity of the differential input signals and fixing the comparison window with only one reference level; 4) splitting the level-crossing detections. Designed to be implemented in 0.18 µm CMOS technology, the proposed ADC achieves 8 bits of resolution with much lower power consumption than conventional LC-ADCs.

This paper presents an implementation of a least voltage drop neural biphasic stimulator circuit applied in cochlear implants. Using a double loop negative feedback topology, the output impedance of the current generator is increased, while requiring only one effective drain-source voltage drop (Veff). This allows the circuit to convey more charge into the tissue. The circuit can provide a biphasic stimulation scheme from a single ended supply with an amplitude range of 10µA up to 1.05mA for a wide range of electrode-tissue impedances, RL=1kΩ∼10kΩ, CL=1nF∼10nF. The stimulation current is set by scaling a reference current using a two stage binary-weighted transistor DAC configuration (3 bits HV transistor DAC and 4 bits LV transistor DAC) to improve the speed of stimulation pulses and minimize the area of the circuit. Simulation results, using the AMS 0.18µm high-voltage CMOS process, show that the charge error within a cycle (600µs) is only 0.02%, equivalent to a DC current error of 3nA at the maximum stimulation current with a load of 10kΩ+10nF.

A nano-power 4th-order band-pass filter operating from a 0.5 V supply voltage with an adjustable center frequency, ranging from 250 Hz to 4 kHz (4 octaves), is presented. The filter is constituted from cascadable 2nd-order circuit cells that are realized by a network of three transistors and two capacitors comprising only one branch of bias current. As a result of the compact low voltage circuit architecture, a dynamic range of 52 dB is obtained, which leads to best figure of merit achieved among other existing designs.

This paper presents a modular technique for transconductance reduction of a sub-threshold transconductor. This technique employs an ordinary differential pair circuit as a module to build a linear attenuator and to be the main transconductor. By applying the linear attenuation, the input linear range expansion and transconductance reduction are simultaneously achieved by sacrificing around 33% of its dynamic range compared to the ordinary differential pair transconductor. A 2nd-order Gm-C low-pass as an application of the proposed transconductor has been designed and simulated using 0.18-µm AMS technology. Compared to existing designs, post-layout simulation results show that, with a smaller active area (including bias circuitry, transconductors and capacitors), this design provides greater dynamic range, wider tuning range and lower power consumption.

This paper presents the design of a robust and large range RF energy harvester with a control loop. The harvester is based on an optimally mismatched antenna-rectifier interface that offers a large passive voltage boost to increase the sensitivity of the energy harvester while still extracting energy from the antenna. A control loop is proposed that maximizes the voltage on the storage capacitor by keeping the rectifier at resonance during charging continuously. The basic principle of this loop has been implemented and verified with simulations. The loop is able to optimize the antenna-electronics interface for a ±33% change in antenna reactance. A comparison with state-of-the-art RF energy harvesters shows major improvements in rectified output voltage at power levels lower than -25 dBm.

The subsampling based Software Defined Radio (SuSDR) architecture features low power consumption and reconfigurability. However, the major drawback of the SuSDR is its poor reliability and robustness due to the poor noise performance. Although jitter compensation techniques have been proposed to improve the noise performance of the SuSDR, those methods are very complicated to implement in hardware. Moreover, since the accuracy of the numerical operation is not taken into consideration in those methods, the effectiveness of those compensation methods can be questioned. In this paper, a SuSDR architecture with jitter compensation is proposed, and implementation imperfections like the accuracy of the ADC are taken into account. Using the analysis, the requirements for the ADCs and the reference frequency can be derived from the system specifications, and this will lead to a practical implementation of the proposed architecture. In conclusion, the SuSDR with the proposed jitter compensation technique can be a promising low power, reconfigurable and robust wireless architecture for wireless sensor networks (WSN).

A modified circuit-level strategy to improve the speed/stability trade-off of low-dropout regulators is presented. The technique, called hybrid-cascode compensation, is applied to stabilize the regulation loop. When designed carefully, results prove the efficacy of this method in minimizing output settling time under various transient conditions. Equivalently, power consumption and/or die area can be minimized for the same settling time. Employing this technique, a 0.7V-10mA voltage regulator with a minimum line voltage of IV has been designed in 90nm CMOS technology. With improved settling time, stability is guaranteed for load capacitors as low as 50pF. Power supply rejection is always better than -30dB for all frequencies.

The wide range of wireless body area network (WBAN) applications gives rise to different system requirements for the carrier frequencies and data rates. In order to accommodate various standards in WBAN applications, a universal receiver system with good performance and low power is highly desirable. The subsampling receiver architecture is one of the promising receiver architectures that might fulfill the features of low power consumption and reconfigurability. However, there are two main concerns, namely the frequency stability and noise performance. In order to overcome these problems, a novel subsampling receiver architecture with two sampling branches as well as a new compensation algorithm are proposed and analyzed in this paper. The frequency stability and noise performance of the receivers can be greatly improved using this architecture. Simulation in different scenarios is carried out, and the results verify the effectiveness of the proposed architecture.

According to recent physiological experiments, the envelope and phase of speech signals are required to enhance the perceptive capability of a cochlear implant processor. In this paper, the design of an analog complex gammatone filter is introduced in order to extract both envelope and phase information of the incoming speech signals as well as to emulate the basilar membrane spectral selectivity. The gammatone impulse response is first transformed into the frequency domain and the resulting 8th-order transfer function is subsequently mapped onto a state-space description of an orthonormal ladder filter. Using this approach, the real and imaginary transfer functions that share the same denominator can be extracted using two different C matrices. This results in a compact filter structure. The proposed filter is designed using Gm-C integrators and sub-threshold CMOS devices in AMIS 0.35 μm technology. Simulation results using Cadence RF Spectre confirm the design principle and ultra low power operation.

An ultra low-power, high linearity, wide swing, current sample-and-hold circuit is presented. The proposed circuit employs negative feedback, provides very low switching error and allows for class-AB operation. Sub-threshold CMOS devices are employed to realize all circuit building blocks which leads to ultra low power consumption and large dynamic range. Operating from a 0.65V supply, simulation results using TSMC 0.13μm CMOS model parameters confirm that the proposed circuit consumes 24nW static power and for 20kS/s sampling rate, a dynamic range and a signal to noise plus distortion ratio larger than 70dB are achieved.

An LC filter based UWB pulse generator to be implemented in IBM 0.13 μm CMOS technology is presented. A 6thorder elliptical filter approximation of the Federal Communications Commission (FCC) Ultra Wide Band (UWB) mask is used to generate the transfer function. The filter order is chosen based on mask filling efficiency, component spread and circuit complexity. The impulse response of the filter is used to generate the UWB pulse. The current consumption is 2.8 mA at 1.5 V, at a pulse rate of 200 MHz. The bandwidth of the UWB pulse is 4GHz. The pulse generator operates over the military temperature range (-40°C to 125°C). Monte Carlo analysis simulation results show an acceptable effect of both mismatch and process variations on the UWB pulse.

To handle the 12dB peak-to-average-power ratio (PAPR) of OFDM signals in a 802.11a/g WLAN receiver baseband, an instantaneously companding system consisting of a 5-order low pass SC filter and a 10-bit pipeline ADC is presented. The filter cut-off and clock frequencies are 10MHz and 100MHz respectively and the ADC sampling frequency is 25MS/s. The filter provides the compressed output directly to the ADC and the signal expansion is done in the digital domain, which eliminates the need of an analog expansion amplifier. For a 12dB increase in dynamic range, it is estimated that the filter consumes 3.7 times less power than a conventional filter while the dynamic range required from the ADC is reduced by 12dB due to companding by a factor of 4. The filter and the ADC are designed to be implemented in a 1.2V, IBM 0.13μm CMOS process and the total power consumption is 75mW.

Abstract — Successive-approximation analog-to-digital converters (SA-ADCs) have recently been widely used for moderate-speed moderate-resolution applications where power consumption is of major concern. In this paper, several techniques are proposed to further reduce the power consumption of an SA-ADC. These solutions include a split-segmented architecture for the capacitor-based digital-to-analog converter (DAC), a modified switching scheme for the DAC, and employing a smaller supply voltage for the comparator and the successive-approximation register while using a new power-efficient digital level converter. Spectre simulation results of a single-ended 10-bit 100kS/s SA-ADC in a 0.13-µm CMOS technology employing the proposed techniques show that the ADC (excluding reference buffers) consumes less than 1 µW of power while offering an effective number of bits of 9.2. I.

In order to realize a nano-power wavelet filter for biomedical applications, this paper applies the Singular Value Decomposition approximation to transform the time domain 1st-derivative of a Gaussian (gauss1) wavelet base into a 5th-order z-domain transfer function. Consequently, to realize the approximated transfer function in CMOS technology employing circuitry that operates from a low supply voltage, a sampled data circuit technique, coined ‘Switched Gain Cell, (SGC),’ is introduced. Using the SGC technique, standard MOS switches, simple subthreshold (nonlinear) transconductors and their associated parasitic capacitances suffice to constitute the filter, while the scale of the filter can be controlled by the clock frequency. This renders the filter architecture to be simple, modular, and area efficient. Simulation results, using 0.13µm CMOS model parameters, show that the wavelet filter implements the gauss1 wavelet base well, operates from a 1V supply and consumes less than 0.47 µW quiescent power.

A low noise amplifier for UWB and broadband applications is presented. The active dual loop negative feedback architecture dissevers the severe tradeoff existing between the input impedance, gain and noise figure, and produces a flat S11across the entire band. The LNA is composed of a voltage amplifying negative feedback amplifier with a transconductance amplifier forming a shunt-shunt feedback around it, thereby tailoring the input impedance with respect to the gain settings of the first amplifier. The values of the resistive feedback elements have been chosen such that they fulfill the requirements of gain, input impedance, noise figure and linearity. The design has been carried out in TSMC 0.13 mum CMOS technology. From circuit simulations, the average gain of the LNA across 2-7 GHz is 13 dB. The noise figure is below 4 dB with a minimum of 2.9 dB. S11is below -15 dB for the entire frequency band. The design employs a DC-current re-use scheme to reduce the power consumption. The LNA draws 5.6 mA from a 1.2 V supply.

This paper presents a time-interleaved sampling delay circuit to be used in an autocorrelation receiver for impulse-radio UWB. It applies a 10 GHz time-interleaved sampling and readout operation for analog signal storage and reconstruction. The delay function is achieved by shifting the sampling and reading clock sequence by a particular time interval. System analysis shows the feasibility of using sampling operation in the delay without losing autocorrelation information, and gives design suggestions for the circuits. The delay circuit has been designed to be implemented in TSMC 0.13 um CMOS technology. Simulation results predict a 500 ps delay at a power consumption of 10 mW from a 1.2 V power supply. Moreover, the delay range from 100 ps to 900 ps can be covered in 100 ps steps without additional power consumption.

A low-noise amplifier for ultra wide band (UWB) applications is presented. The use of a dual-loop negative feedback topology is advantageous, since it allows to achieve both impedance matching and a very low noise figure, and saves a lot of chip area as no bulky inductors are needed. A nullor and a resistive feedback network are employed, and the values of the feedback elements involved are defined in order to fulfill the noise-figure, input impedance and power-gain requirements for an UWB receiver. To ensure circuit stability, frequency compensation is done by means of a phantom zero and the addition of a transistor connected between input and output, thus realizing a multipath structure. The design targets UMC 0.13mufrac14m CMOS IC technology and operation from a 1.2-volt supply. From circuit simulations, the power gain of the LNA amounts to 17dB, and the bandwidth spans up to 12 GHz. Su is below -lOdB up to 10 GHz and the noise figure is below 3dB up to 8 GHz, and below 4dB@10 GHz. The power consumption equals 14 mA. Compared to competitive solutions, using resonating load stages or LC ladder networks, this chip will be much smaller and cheaper; it will use standard CMOS technology, and achieve very low noise, high gain and wide band matching at reasonable power consumption.

In this paper, system level design techniques for companding baseband switched capacitor (SC) filters for WLAN applications are presented. With companding, no AGC is required in front of the filter. A filter prototype is designed for 802.11g receiver and simulation results show that, with careful design of the opamps, a total harmonic distortion of less than 0.5% can be achieved. A new type of companding ADCs along with the algorithm to achieve companding in ADCs is proposed. It is shown that companding by a factor of 4 reduces the power consumption of the SC filter by a factor close to 4 times for a given dynamic range whereas it directly results in 12 dB reduction in the dynamic range requirement of the following ADC.

In Haddad et al. (2004), we have shown that it is feasible to design filters with arbitrary waveform responses and therefore we propose an ultra-wideband pulse generator incorporating a filter with a Daubechies' impulse response (i.e. maximally flat over the desired frequency range). This pulse generator is co-designed with wideband antennas. An eight-order Pade approximation of its transfer function is selected to implement the FCC stipulated frequency spectrum. Subsequently, the orthonormal (Johns et al., 1989) form is adopted, which is intrinsically semi-optimized for dynamic range, has low sensitivity to component mismatch, high sparsity and whose coefficients can be physically implemented. Each coefficient in the state-space description of the orthonormal ladder filter is implemented at circuit level using a novel 2-stage gm cell employing negative feedback. Simulation results in IBM's CMOS 0.13mum technology show that this pulse generator requires a total current of 25mA from a 1.2V power supply. The frequency coverage of the simulated waveform is about 85% of the FCC mask

The frequency-domain exponential transfer function of a delay function cannot be realized with a finite number of lumped elements. Therefore an approximation of a rational quotient of polynomials has to be used. While the use of Bessel polynomials results in the well-known all-pole Bessel-Thomson approximation, a Taylor expansion of the exponential transfer function of a delay around one point results in another type of rational transfer, known as Pade approximation. Although a Bessel-Thomson approximation results in an overshoot-free step response it has slower response and smaller bandwidth in comparison to a Pade-approximated delay. Unfortunately, the latter suffers from overshoot. To reduce the overshoot but preserve the fast-response and large-bandwidth properties, a new delay approximation method is introduced. The method is based on approximation of the delta time-domain response of an ideal delay by a narrow Gaussian time-domain impulse response. The subsequent Pade approximation of the corresponding Gaussian transfer function yields a rational transfer function that is ready for implementation in an analog fashion and realizes a delay with both a large bandwidth and little overshoot

A dual-loop resistive-feedback power-to-current amplifier circuit to be implemented in SiGe or GaAs IC technology is presented. Simulation results indicate that any technology process with NFmin20 GHz is able to achieve an overall noise figure less than 0.5 dB, an input return loss less than -15 dB and flat gain over a frequency range from 0.6 GHz to 1.6 GHz.

This paper describes a method to minimize the total energy necessary to communicate data over a frequency selective fading channel using multicarrier data transmission. The energy is minimized given a desired average bit error rate at a fixed gross bit rate. For a number of configurations, the optimal energy distribution is calculated analytically. For other configurations, we present a generic numerical approach. To evaluate the performance, a comparison is made with two other commonly used energy assignment schemes. The advantage of this scheme is most apparent when the channel suffers from deep fades, as is the case in mobile wireless communications.

Nonlinear distortion of OFDM signals can significantly increase the receiver symbol error rate (SER). Currently, distortion analyses rely on simulation, not yielding insight into the problem, or apply to specific nonlinearities only. In this letter, general analytic results are presented on the errors resulting from distortion. The results are applicable to smooth nonlinear distortion of an OFDM signal, which is the most common distortion. Simple analytical expressions are derived which allows a designer to determine the SER before performing simulations. Further, it is shown that the error on each OFDM subcarrier is approximately equally large.

The influence of bandpass non-linear distortion on an OFDM signal is investigated. The spectrum of the distorted signal and the resulting detection errors are determined. Non-linear distortion of OFDM signals can significantly increase the receiver BER. Previous analyses rely on simulation, or apply to specific non-linearities only. Here, an analysis is presented which is applicable to any weakly non-linear distortion of an OFDM signal. Simple analytical expressions are derived which allow a designer to choose parameters without performing simulations. Further, it is shown that the error on each OFDM subcarrier is approximately equally large.

Non-linear distortion of OFDM signals can significantly increase the receiver BER. Currently, distortion analyses rely on simulation, not yielding insight into the problem, or apply to specific non-linearities only. In this paper, general analytic results are presented on the errors resulting from distortion. The results are applicable to smooth non-linear distortion of an OFDM signal, which is the most common distortion. Simple analytical expressions are derived which allows a designer to determine the BER before performing simulations. Further, it is shown that the error on each OFDM subcarrier is approximately equally large.

A directional hearing aid adapter was designed and implemented using dynamic translinear (DTL) circuit techniques. The signal-processing core was optimized to yield minimum current consumption for the specified dynamic range. In this paper the design and implementation of the core is presented. It consumes a current of 40 /spl mu/A at a supply voltage of down to 1.0 V having a total integrated capacitance of 400 pF for a dynamic range of 50 dB.

This paper presents a topological method for identifying multiple static translinear loops using a graphical representation. It is found that the translinear principle has a new formulation based on graph theory concepts and it is applied to circuits containing BJTs and MOS transistors. In addition, it introduces the concept of translinear circuit for representing a translinear loop. The types of interaction between translinear loops are studied and its properties are established. The method is illustrated with a generic example.

This paper discusses the design of low-voltage low-power fully-integratable automatic gain controls. Four different AGCs are presented, all consisting of three elementary building blocks: a controlled amplifier, a comparator and a voltage follower. Their design is treated separately. As an example, the final section describes an automatic gain control for hearing instruments.>