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M. T. Smith

dblp:49/217 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1987
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 70% Hardware accelerators and domain-specific architectures · 23% Integrated circuit design · 7%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
hardware verification		 0.011987
A Hardware Switch Level Simulator for Large MOS Circuits · DAC 1987
Electronic design automation › circuit simulation › device and circuit simulation
MOS circuit simulation		 0.011987
A Hardware Switch Level Simulator for Large MOS Circuits · DAC 1987
Hardware accelerators and domain-specific architectures › scientific computing accelerator
simulation accelerator		 0.011987
A Hardware Switch Level Simulator for Large MOS Circuits · DAC 1987
Electronic design automation › circuit simulation
switch-level simulation		 0.011987
A Hardware Switch Level Simulator for Large MOS Circuits · DAC 1987
Integrated circuit design › digital circuit design
MOS circuits		 0.011987
A Hardware Switch Level Simulator for Large MOS Circuits · DAC 1987

Methods — techniques the papers use, named apart from their topics

timing simulation · 0.0hardware simulation · 0.0
YearPublicationVenuePosition
1987 A Hardware Switch Level Simulator for Large MOS Circuits
abstract
The HSS is a Hardware Switch level Simulator that has been designed and built to be a useful and cost effective addition to a MOS circuit designers tool set. The HSS is based on the MOSSIM software simulator, but has been further developed to include hardware for simulating pass transistor circuits and for doing timing simulation. By using dynamic RAM for internal list storage, a single HSS processor can accommodate a circuit of up to 262,144 MOS devices. The HSS can be interfaced to a variety of host computers via a general purpose parallel interface, and in its current form offers a 25 times speed improvement compared to MOSSIM II running on a VAX 11-780. Timing mode offers similar speed advantages, with delay calculations that are sufficiently accurate for many simulation tasks.
M. T. Smith
 DAC1