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Tomoyuki Ishii

dblp:49/2234 · DBLP profile ↗
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3ranked-venue papers
0as first author
0since 2021 · last 2003
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 1Systems, architecture and hardware · 1Graphics, computer vision, multimedia, augmented reality and games · 1Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Artificial intelligence
1 paper
Robot manipulation · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 50% Memory systems · 38% Hardware reliability and fault tolerance · 12%

Topics — the 4 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Robotics › Robot manipulation › redundant manipulator
hyper-redundant manipulator
0.012003
Float Arm V: Hyper-Redundant Manipulator with Wire-Driven Weight-Compensation Mechanism · ICRA 2003
Robotics › Robot manipulation › robot design › static balancing
weight compensation mechanism
0.012003
Float Arm V: Hyper-Redundant Manipulator with Wire-Driven Weight-Compensation Mechanism · ICRA 2003
Integrated circuit design › memory circuit design
memory cell design
0.011999
Single-electron memory for giga-to-tera bit storage · Proc. IEEE 1999
Memory systems
non-volatile memory
0.011999
Single-electron memory for giga-to-tera bit storage · Proc. IEEE 1999

Methods — techniques the papers use, named apart from their topics

wire-driven mechanism · 0.0parallelogram linkage · 0.0
YearPublicationVenuePosition
2003 Float Arm V: Hyper-Redundant Manipulator with Wire-Driven Weight-Compensation Mechanism
abstract
In this paper, the wire-driven weight-compensation mechanism is proposed. This mechanism consists of a parallelogram linkage mechanism that has an extended portion with the wired double pulley. This is a lighter solution compared to others since no springs are utilized. Below, a detailed description of this new weight-compensation mechanism and performances of Float Arm V with this new mechanism are given.
Shigeo Hirose, Tomoyuki Ishii, Atsuo Haishi
ICRA2
2001 An Associate Memory Model Of Facial Expressions And Its Application In Facial Expression Recognition Of Patients On Bed
abstract
In this paper, we proposed a new method of monitoring patients on bed by utilizing the facial expression analyses and recognition. In this proposed method, the optical flows of the corresponding image sequence, which appeard the facial actions, were computed. Based on the optical flow projection histogram on and coordinate axes in the mouth region and the eye region, the facial action features were extracted. By utilizing the facial action feature rate of occurrence on the happiness, easiness, uneasiness, disgust, suffering and surprise, the associate memory model of facial expressions is composed to recognize the facial expressions. The classification performance of our associate memory model is demonstrated by using a training set and a testing set from the facial expression database made for our research project.
Yoshitaka Shibata, Tomoyuki Ishii, Koji Hashimoto, K. Katamachi, K. Noguchi, N. Kakizaki, Dawei Cai
ICME3
1999 Single-electron memory for giga-to-tera bit storage
abstract
Starting with a brief review on the single-electron memory and its significance among various single-electron devices, this paper addresses the key issues which one inevitably encounters when one tries to achieve giga-to-tera bit memory integration. Among the issues discussed are: room-temperature operation; memory-cell architecture; sensing scheme; cell-design guideline; use of nanocrystalline silicon versus lithography; array architecture; device-to-device variations; read/write error rate; and CMOS/single-electron-memory hybrid integration and its positioning among various memory architectures.
Kazuo Yano, Tomoyuki Ishii, Toshiaki Sano, Toshiyuki Mine, Fumio Murai, Takashi Hashimoto, Takashi Kobayashi 0002, Tokuo Kure, Koichi Seki
Proc. IEEE2