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Dimitris Syrivelis

dblp:49/2621 · DBLP profile ↗
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19ranked-venue papers
2as first author
3since 2021 · last 2024
0000-0002-2344-5665ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 9 · 1 first-authorSystems, architecture and hardware · 8 · 1 first-author · 2 since 2021Software engineering, systems software and programming languages · 2Security and privacy · 1Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer networks
6 papers
Internet architecture and protocols · 22% Edge and fog computing · 18% Internet of things and sensor networks · 18%
Computer architecture, parallel and distributed computing, and storage systems
3 papers
Cloud and datacenter computing · 50% Memory systems · 46% Reconfigurable computing and FPGAs · 3%

Topics — the 21 heaviest of 25, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Edge and fog computing
collaborative edge computing
0.812024
EMPYREAN: Trustworthy, Cognitive and AI-driven Collaborative Associations of IoT Devices and Edge Resources for Data Processing · HPDC 2024
Internet of things and sensor networks
iot devices
0.812024
EMPYREAN: Trustworthy, Cognitive and AI-driven Collaborative Associations of IoT Devices and Edge Resources for Data Processing · HPDC 2024
Internet architecture and protocols
network coding
0.532016
A Policy-Aware Enforcement Logic for Appropriately Invoking Network Coding · IEEE/ACM Trans. Netw. 2016
Wireless network coding: Deciding when to flip the switch · INFOCOM 2013
A Framework for Joint Network Coding and Transmission Rate Control in Wireless Networks · INFOCOM 2010
Cloud and datacenter computing › resource management
datacenter resource management
0.412020
ThymesisFlow: A Software-Defined, HW/SW co-Designed Interconnect Stack for Rack-Scale Memory Disaggregation · MICRO 2020
Memory systems
memory disaggregation
0.412020
ThymesisFlow: A Software-Defined, HW/SW co-Designed Interconnect Stack for Rack-Scale Memory Disaggregation · MICRO 2020
Memory systems › memory disaggregation › memory pooling
rack-scale memory pooling
0.412020
ThymesisFlow: A Software-Defined, HW/SW co-Designed Interconnect Stack for Rack-Scale Memory Disaggregation · MICRO 2020
Cloud and datacenter computing
resource disaggregation
0.412020
ThymesisFlow: A Software-Defined, HW/SW co-Designed Interconnect Stack for Rack-Scale Memory Disaggregation · MICRO 2020
Internet architecture and protocols › network coding
coding-aware routing
0.212016
A Policy-Aware Enforcement Logic for Appropriately Invoking Network Coding · IEEE/ACM Trans. Netw. 2016
Wireless networking › wireless network optimization
throughput optimization
0.212016
A Policy-Aware Enforcement Logic for Appropriately Invoking Network Coding · IEEE/ACM Trans. Netw. 2016
Wireless networking
wireless network protocols
0.212016
A Policy-Aware Enforcement Logic for Appropriately Invoking Network Coding · IEEE/ACM Trans. Netw. 2016
Network optimization and economics › game theory › cooperative game theory
coalitional game
0.212015
Bits and coins: Supporting collaborative consumption of mobile internet · INFOCOM 2015
Network optimization and economics
resource allocation
0.212015
Bits and coins: Supporting collaborative consumption of mobile internet · INFOCOM 2015
Network optimization and economics
resource sharing
0.212015
Bits and coins: Supporting collaborative consumption of mobile internet · INFOCOM 2015
Network performance modeling
throughput analysis
0.212013
Wireless network coding: Deciding when to flip the switch · INFOCOM 2013
Internet architecture and protocols › network coding
wireless network coding
0.212013
Realizing the Benefits of Wireless Network Coding in Multirate Settings · IEEE/ACM Trans. Netw. 2013
Memory systems
memory interconnect
0.112020
ThymesisFlow: A Software-Defined, HW/SW co-Designed Interconnect Stack for Rack-Scale Memory Disaggregation · MICRO 2020
Routing and switching › routing › packet routing
store-and-forward routing
0.122016
A Policy-Aware Enforcement Logic for Appropriately Invoking Network Coding · IEEE/ACM Trans. Netw. 2016
Wireless network coding: Deciding when to flip the switch · INFOCOM 2013
Transport protocols and congestion control › rate control
transmission rate control
0.112010
A Framework for Joint Network Coding and Transmission Rate Control in Wireless Networks · INFOCOM 2010
Cellular and mobile networks
mobile terminals
0.112015
Bits and coins: Supporting collaborative consumption of mobile internet · INFOCOM 2015
Wireless networking › link adaptation
rate adaptation
0.012013
Realizing the Benefits of Wireless Network Coding in Multirate Settings · IEEE/ACM Trans. Netw. 2013
Routing and switching
routing
0.012013
Wireless network coding: Deciding when to flip the switch · INFOCOM 2013

Methods — techniques the papers use, named apart from their topics

federated learning · 1.5AI workload processing · 1.5hardware-software co-design · 0.4analytical modeling · 0.4testbed implementation · 0.3distributed algorithm · 0.3testbed experimentation · 0.2ns-3 simulation · 0.2software-defined networking · 0.2coalitional game theory · 0.2testbed experiments · 0.2
YearPublicationVenuePosition
2024 EMPYREAN: Trustworthy, Cognitive and AI-driven Collaborative Associations of IoT Devices and Edge Resources for Data Processing
abstract
The EU-funded EMPYREAN project (empyrean-horizon.eu) aims to establish a hyper-distributed computing paradigm, leveraging collaborative, heterogeneous IoT devices and federated resources. EMPYREAN focuses on developing technologies for efficient AI workload processing, secure distributed edge storage and cloud-native application development. It will offer open and standardised APIs and use open-source platforms. EMPYREAN's capabilities will be demonstrated through three use cases: advanced manufacturing, smart agriculture, and warehouse automation.
Aristotelis Kretsis, Panagiotis C. Kokkinos, Emmanouel A. Varvarigos, Dimitris Syrivelis, Paraskevas Bakopoulos, Márton Sipos, Marcell Fehér, Daniel Enrique Lucani, José Manuel Bernabé Murcia, Antonio F. Skarmeta, Ivan Paez, Luca Cominardi, Michael Mercier, Pedro Velho, Yiannis Georgiou 0002, Charalampos Mainas, Anastassios Nanos, Javier Martin, Aitor Fernández Gómez, Roberto Gonzalez, Panos Ilias, Theodoros Chalazas, Keshav Chintamani
HPDC4
2022 Exploiting HBM on FPGAs for Data Processing
abstract
Field Programmable Gate Arrays (FPGAs) are increasingly being used in data centers and the cloud due to their potential to accelerate certain workloads as well as for their architectural flexibility, since they can be used as accelerators, smart-NICs, or stand-alone processors. To meet the challenges posed by these new use cases, FPGAs are quickly evolving in terms of their capabilities and organization. The utilization of High Bandwidth Memory (HBM) in FPGA devices is one recent example of such a trend. In this article, we study the potential of FPGAs equipped with HBM from a data analytics perspective. We consider three workloads common in analytics-oriented databases and implement them on an FPGA showing in which cases they benefit from HBM: range selection, hash join, and stochastic gradient descent for linear model training. We integrate our designs into a columnar database (MonetDB) and show the trade-offs arising from the integration related to data movement and partitioning. We consider two possible configurations of the HBM, using a single and a dual clock version design. With the right design, FPGA+HBM-based solutions are able to surpass the highest performance provided by either a two-socket POWER9 1 system or a 14-core Xeon 2 E5 by up to 5.9× (range selection), 18.3× (hash join), and 6.1× (SGD).
Runbin Shi, Kaan Kara, Christoph Hagleitner, Dionysios Diamantopoulos, Dimitris Syrivelis, Gustavo Alonso
ACM Trans. Reconfigurable Technol. Syst.5
2021 Energy-Aware Learning Agent (EALA) for Disaggregated Cloud Scheduling
abstract
Cloud data centers require enormous amounts of energy to run their clusters of computers. There are huge financial and environmental incentives for cloud service providers to increase their energy efficiency without causing significant negative impacts on their customers' qualities of experience. Increasing resource utilization reduces energy consumption by consolidating workloads on fewer machines and allows cloud service providers to turn off inactive devices. While traditional architectures only allow virtual machines (VMs) to use the memory and CPU resources of a single device, VMs in a disaggregated cloud can utilize the small residual capacities of multiple separate devices. Separating VM resources across multiple devices leads to severe fragmentation that eventually negates any positive impact disaggregation has on utilization. To address the fragmentation problem, we present a method of ensuring a cloud operates using the minimal number of devices over time. Here we introduce an Energy-Aware Learning Agent (EALA) that uses reinforcement learning to guarantee the system can meet minimal quality of service requirements and provide energy savings without the need for VM migration. We evaluate the use of EALA guiding the decisions of Best-Fit compared to vanilla Best-Fit using the Google cluster trace. We show that EALA improves utilization by 2% and reduces the number of times that compute nodes switch on and off by 11% compared to vanilla Best-Fit.
Nick Nordlund, Vassilis Vassiliadis, Michele Gazzetti, Dimitris Syrivelis, Leandros Tassiulas
CLOUD4
2020 High Bandwidth Memory on FPGAs: A Data Analytics Perspective
abstract
FPGA-based data processing in datacenters is increasing in popularity due to the demands of modern workloads and the resulting need for specialization in hardware. Driven by this trend, vendors are rapidly adapting reconfigurable devices to suit data and compute intensive workloads. Inclusion of High Bandwidth Memory (HBM) in FPGA devices is a recent example. HBM promises overcoming the bandwidth bottleneck, often faced by FPGA-based accelerators due to their throughput oriented design. In this paper, we study the usage and benefits of HBM on FPGAs from a data analytics perspective. We consider three workloads that are often performed in analytics oriented databases and implement them on FPGA showing in which cases they benefit from HBM: range selection, hash join, and stochastic gradient descent for linear model training. We integrate our designs into a columnar database (MonetDB) and show the trade-offs arising from the integration related to data movement and partitioning. In certain cases, FPGA+HBM based solutions are able to surpass the highest performance provided by either a 2-socket POWER9 system or a 14-core XeonE5 by up to 1.8x (selection), 12.9x (join), and 3.2x (SGD).
Kaan Kara, Christoph Hagleitner, Dionysios Diamantopoulos, Dimitris Syrivelis, Gustavo Alonso
FPL4
2020 ThymesisFlow: A Software-Defined, HW/SW co-Designed Interconnect Stack for Rack-Scale Memory Disaggregation
abstract
With cloud providers constantly seeking the best infrastructure trade-off between performance delivered to customers and overall energy/utilization efficiency of their data-centres, hardware disaggregation comes in as a new paradigm for dynamically adapting the data-centre infrastructure to the characteristics of the running workloads. Such an adaptation enables an unprecedented level of efficiency both from the standpoint of energy and the utilization of system resources. In this paper, we present - ThymesisFlow - the first, to our knowledge, full-stack prototype of the holy-grail of disaggregation of compute resources: pooling of remote system memory. Thymesis-Flow implements a HW/SW co-designed memory disaggregation interconnect on top of the POWER9 architecture, by directly interfacing the memory bus via the OpenCAPI port. We use ThymesisFlow to evaluate how disaggregated memory impacts a set of cloud workloads, and we show that for many of them the performance degradation is negligible. For those cases that are severely impacted, we offer insights on the underlying causes and viable cross-stack mitigation paths.
Christian Pinto, Dimitris Syrivelis, Michele Gazzetti, Panos K. Koutsovasilis, Andrea Reale, Kostas Katrinis, H. Peter Hofstee
MICRO2
2018 REMAP: Remote mEmory Manager for disAggregated Platforms
abstract
Disaggregated computing is a new approach that promises to alleviate the problem of fixed resource proportionality in datacenter deployments. Two critical factors that affect the overall performance of disaggregated platforms are remote memory access latency and throughput. Previous works primarily expose remote data processing at the applcation level that (a) require code annotations and/or the use of custom user-level libraries, and (b) may hinder the overall system protection and functionality. In this paper, we are taking a different approach: we propose the Remote mEmory Manager for dis-Aggregated Platforms (REMAP), a hardware architecture that enables the hotplug of remote memory resources to processing nodes, as normal paged memory at the OS-level, without requiring application-level code modifications. REMAP tightly couples processing nodes with remote memory controllers. Our architecture “expands” system memory on demand, by dynamically attaching remote memory modules to unused Local Physical Address (LPA) ranges, where the memory access requests are tunneled over high-speed, low-latency serial links. To evaluate REMAP in terms of performance, we implemented a prototype using two zcul02 FPGA boards. REMAP provides a remote cache-line access latency of less than 750 nsec, and up to 1.3× overall system throughput, compared to a baseline CPU-memory configuration.
Dimitris Theodoropoulos 0001, Andrea Reale, Dimitris Syrivelis, Maciej Bielski, Nikolaos Alachiotis 0001, Dionisios N. Pnevmatikatos
ASAP3
2018 dReDBox: Materializing a full-stack rack-scale system prototype of a next-generation disaggregated datacenter
abstract
Current datacenters are based on server machines, whose mainboard and hardware components form the baseline, monolithic building block that the rest of the system software, middleware and application stack are built upon. This leads to the following limitations: (a) resource proportionality of a multi-tray system is bounded by the basic building block (mainboard), (b) resource allocation to processes or virtual machines (VMs) is bounded by the available resources within the boundary of the mainboard, leading to spare resource fragmentation and inefficiencies, and (c) upgrades must be applied to each and every server even when only a specific component needs to be upgraded. The dRedBox project (Disaggregated Recursive Datacentre-in-a-Box) addresses the above limitations, and proposes the next generation, low-power, across form-factor datacenters, departing from the paradigm of the mainboard-as-a-unit and enabling the creation of function-block-as-a-unit. Hardware-level disaggregation and software-defined wiring of resources is supported by a full-fledged Type-1 hypervisor that can execute commodity virtual machines, which communicate over a low-latency and high-throughput software-defined optical network. To evaluate its novel approach, dRedBox will demonstrate application execution in the domains of network functions virtualization, infrastructure analytics, and real-time video surveillance.
Maciej Bielski, Ilias Syrigos, Kostas Katrinis, Dimitris Syrivelis, Andrea Reale, Dimitris Theodoropoulos 0001, Nikolaos Alachiotis 0001, Dionisios N. Pnevmatikatos, E. H. Pap, Georgios Zervas, Vaibhawa Mishra, Arsalan Saljoghei, Alvise Rigo, Jose Fernando Zazo, Sergio López-Buedo, Martí Torrents, Ferad Zyulkyarov, Michael Enrico, Óscar González de Dios
DATE4
2017 Design and implementation of a belief-propagation scheduler for multicast traffic in input-queued switches
Paolo Giaccone, Marco Pretti, Dimitris Syrivelis, Iordanis Koutsopoulos, Leandros Tassiulas
Comput. Commun.3
2016 Rack-scale disaggregated cloud data centers: The dReDBox project vision
Kostas Katrinis, Dimitris Syrivelis, Dionisios N. Pnevmatikatos, Georgios Zervas, Dimitris Theodoropoulos 0001, Iordanis Koutsopoulos, K. Hasharoni, Daniel Raho, Christian Pinto, Felix Espina, Sergio López-Buedo, Qianqiao Chen, Mario Nemirovsky, Damian Roca, H. Klos, T. Berends
DATE2
2016 A Policy-Aware Enforcement Logic for Appropriately Invoking Network Coding
abstract
Network coding has been shown to offer significant throughput benefits over certain wireless network topologies. However, the application of network coding may not always improve the network performance. In this paper, we first provide an analytical study, which helps in assessing when network coding is preferable to a traditional store-and-forward approach. Interestingly, our study reveals that in many topological scenarios, network coding can in fact hurt the throughput performance; in such scenarios, applying the store-and-forward approach leads to higher network throughput. We validate our analytical findings via extensive testbed experiments. Guided by our findings as our primary contribution, we design and implement PACE, a Policy-Aware Coding Enforcement logic that enables network coding only when it is expected to offer performance benefits. Specifically, PACE leverages a minimal set of periodic link quality measurements in order to make per-flow online decisions with regards to when network coding should be activated, and when store-and-forward is preferable. It can be easily embedded into network-coding-aware routers as a user-level or kernel-level software utility. We evaluate the efficacy of PACE via: 1) ns-3 simulations, and 2) experiments on a wireless testbed. We observe that our scheme wisely activates network coding only when appropriate, thereby improving the total network throughput by as much as 350% in some scenarios.
Ahmed Atya, Ioannis Broustis, Shailendra Singh 0004, Dimitris Syrivelis, Srikanth V. Krishnamurthy, Thomas La Porta
IEEE/ACM Trans. Netw.4
2015 Bits and coins: Supporting collaborative consumption of mobile internet
abstract
The recent mobile data explosion has increased the interest for mobile user-provided networks (MUPNs), where users share their Internet access by exploiting the diversity in their needs and resource availability. Although promising, MUPNs raise unique challenges. Namely, the success of such services relies on user participation which in turn can be achieved on the basis of a fair and efficient resource (i.e., Internet access and battery energy) exchange policy. The latter should be devised and imposed in a very fast time scale, based on near real-time feedback from mobile users regarding their needs, resources, and network conditions that are rapidly changing. To address these challenges we design and implement a novel cloud-controlled MUPN system, that employs software defined networking support on mobile terminals, to dynamically apply data forwarding policies with adaptive flow-control. We devise these policies by solving a coalitional game that is played among the users. We prove that the game has a non-empty core and hence the solution, which determines the servicing policy, incentivizes the users to participate. Finally, we evaluate the performance of the service in a prototype, where we investigate its performance limits, quantify the implementation overheads, and justify our architecture design choices.
Dimitris Syrivelis, George Iosifidis, Dimosthenis Delimpasis, Kostas Chounos, Thanasis Korakis, Leandros Tassiulas
INFOCOM1
2013 Wireless network coding: Deciding when to flip the switch
abstract
Network coding has been shown to offer significant throughput benefits over store-and-forward routing in certain wireless network topologies. However, the application of network coding may not always improve the network performance. In this paper1, we provide a comprehensive analytical study, which helps in assessing when network coding is preferable to a traditional store-and-forward approach. Interestingly, our study reveals that in many topological scenarios, network coding can in fact hurt the throughput performance; in such scenarios, applying the store-and-forward approach leads to higher network throughput. We validate our analytical findings via extensive testbed experiments, and we extract guidelines on when network coding should be applied instead of store-and-forward.
Ahmed Atya, Ioannis Broustis, Shailendra Singh 0004, Dimitris Syrivelis, Srikanth V. Krishnamurthy, Thomas La Porta
INFOCOM4
2013 Implementation and evaluation of an information-centric network
George Parisis, Dirk Trossen, Dimitris Syrivelis
Networking3
2013 Realizing the Benefits of Wireless Network Coding in Multirate Settings
abstract
Network coding has been proposed as a technique that can potentially increase the transport capacity of a wireless network via mixing data packets at intermediate routers. However, most previous studies either assume a fixed transmission rate or do not consider the impact of using diverse rates on the network coding gain. Since in many cases, network coding implicitly relies on overhearing, the choice of the transmission rate has a big impact on the achievable gains. The use of higher rates works in favor of increasing the native throughput. However, it may in many cases work against effective overhearing. In other words, there is a tension between the achievable network coding gain and the inherent rate gain possible on a link. In this paper, our goal is to drive the network toward achieving the best tradeoff between these two contradictory effects. We design a distributed framework that: facilitates the choice of the best rate on each link while considering the need for overhearing; and dictates the choice of which decoding recipient will acknowledge the reception of an encoded packet. We demonstrate that both of these features contribute significantly toward gains in throughput. We extensively simulate our framework in a variety of topological settings. We also fully implement it on real hardware and demonstrate its applicability and performance gains via proof-of-concept experiments on our wireless testbed. We show that our framework yields throughput gains of up to 390% as compared to what is achieved in a rate-unaware network coding framework.
Tae-Suk Kim, Ioannis Broustis, Serdar Vural, Dimitris Syrivelis, Shailendra Singh 0004, Srikanth V. Krishnamurthy, Thomas La Porta
IEEE/ACM Trans. Netw.4
2011 A software framework for alleviating the effects of MAC-aware jamming attacks in wireless access networks
Ioannis Broustis, Konstantinos Pelechrinis, Dimitris Syrivelis, Srikanth V. Krishnamurthy, Leandros Tassiulas
Wirel. Networks3
2010 A Framework for Joint Network Coding and Transmission Rate Control in Wireless Networks
abstract
Network coding has been proposed as a technique that can potentially increase the transport capacity of a wireless network via processing and mixing of data packets at intermediate routers. However, most previous studies either assume a fixed transmission rate or do not consider the impact of using diverse rates on the network coding gain. Since in many cases, network coding implicitly relies on overhearing, the choice of the transmission rate has a big impact on the achievable gains. The use of higher rates works in favor of increasing the native throughput; however, it may in many cases work against effective overhearing. In other words, there is a tension between the achievable network coding gain and the inherent rate gain possible on a link. In this paper our goal is to drive the network towards achieving the best trade-off between these two contradictory effects. Towards this, we design a distributed framework that (a) facilitates the choice of the best rate on each link while considering the need for overhearing and (b) dictates the choice of which decoding recipient will acknowledge the reception of an encoded packet. We demonstrate that both of these features contribute significantly towards gains in throughput. We extensively simulate our framework in a variety of topological settings. We also fully implement it on real hardware and demonstrate its applicability and performance gains via proof-of-concept experiments on our wireless testbed. We show that our framework yields throughput gains of up to 390% as compared to what is achieved in a rate-unaware network coding framework.
Tae-Suk Kim, Serdar Vural, Ioannis Broustis, Dimitris Syrivelis, Srikanth V. Krishnamurthy, Thomas La Porta
INFOCOM4
2010 Quantifying the Overhead Due to Routing Probes in Multi-Rate WMNs
abstract
The selection of high-throughput routes is a key element towards improving the performance of wireless multihop networks. While several routing metrics have been proposed in the literature, it has been shown that link-quality aware metrics can provide significantly higher end-to-end throughput. To date, the online computation of such metrics requires the periodic transmission of probe packets at all available transmission rates. However, our link level measurement study on two different 802.11 testbeds demonstrates that: (a) multi-rate probe transmissions increase the number of collisions and enforce nodes to reside in the back-off state for prolonged time periods, and (b) the extent of performance degradation depends on the network density; a network-wide throughput reduction of the order of 400% is possible. In addition, our measurements show that the impact of probing in terms of end-to-end performance can be devastating. In particular, the probing functionality can pose a significant degradation in the end-to-end throughput of a single flow, by at least 35% and as high as 90%, depending on the probing frequency and network density. Finally, we discuss different alternatives to multi-rate probing for the online computation of such metrics.
Ioannis Broustis, Konstantinos Pelechrinis, Dimitris Syrivelis, Srikanth V. Krishnamurthy, Leandros Tassiulas
WCNC3
2009 FIJI: Fighting Implicit Jamming in 802.11 WLANs
Ioannis Broustis, Konstantinos Pelechrinis, Dimitris Syrivelis, Srikanth V. Krishnamurthy, Leandros Tassiulas
SecureComm3
2006 System- and Application-level Support for Runtime Hardware Reconfiguration on SoC Platforms
Dimitris Syrivelis, Spyros Lalis
USENIX ATC, General Track1