Demo Data from EDBT 2026 / reviewers in the wild / expert
Fabio Romeo
dblp:49/2694
· DBLP profile ↗
4ranked-venue papers
1as first author
0since 2021 · last 1991
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3Theory of computation · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Electronic design automation · 85% Parallel and multicore computing · 15% |
Topics — the 11 heaviest of 11, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
physical design |
0.0 | 3 | 1988 | Techniques for multilayer channel routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1988 A Parallel Simulated Annealing Algorithm for the Placement of Macro-Cells · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987 Chameleon: a new multi-layer channel router · DAC 1986 |
Electronic design automation › physical design › routing › wire routing
maze routing |
0.0 | 2 | 1988 | Techniques for multilayer channel routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1988 Chameleon: a new multi-layer channel router · DAC 1986 |
Electronic design automation › physical design › routing › channel routing
multilayer channel routing |
0.0 | 1 | 1988 | Techniques for multilayer channel routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1988 |
Electronic design automation › physical design
routing |
0.0 | 1 | 1988 | Techniques for multilayer channel routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1988 |
Electronic design automation › physical design › placement › module placement
macro placement |
0.0 | 1 | 1987 | A Parallel Simulated Annealing Algorithm for the Placement of Macro-Cells · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987 |
Parallel and multicore computing
parallel algorithms |
0.0 | 1 | 1987 | A Parallel Simulated Annealing Algorithm for the Placement of Macro-Cells · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987 |
Parallel and multicore computing › parallel algorithms › parallel combinatorial optimization
parallel simulated annealing |
0.0 | 1 | 1987 | A Parallel Simulated Annealing Algorithm for the Placement of Macro-Cells · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987 |
Electronic design automation › physical design
placement |
0.0 | 1 | 1987 | A Parallel Simulated Annealing Algorithm for the Placement of Macro-Cells · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987 |
Electronic design automation › physical design › routing
channel routing |
0.0 | 1 | 1986 | Chameleon: a new multi-layer channel router · DAC 1986 |
Electronic design automation › physical design › routing
detailed routing |
0.0 | 1 | 1986 | Chameleon: a new multi-layer channel router · DAC 1986 |
Electronic design automation › physical design › routing
multilayer routing |
0.0 | 1 | 1986 | Chameleon: a new multi-layer channel router · DAC 1986 |
Methods — techniques the papers use, named apart from their topics
three-dimensional maze routing · 0.0simulated annealing · 0.0partitioning · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1991 | A Theoretical Framework for Simulated Annealing
Fabio Romeo, Alberto L. Sangiovanni-Vincentelli |
Algorithmica | 1 |
| 1988 | Techniques for multilayer channel routingabstractThe techniques described have been implemented in a multilayer channel router called Chameleon. Chameleon consists of two stages: a partitioner and a detailed router. The partitioner divides the problems into two-layer and three-layer subproblems such that global channel area is minimized. The detailed router then implements the connections using generalizations of the algorithms used in YACR2 (see ibid., vol.CAD-4, no.3, p.208-19, 1985). In particular, a three-dimensional maze router is used for the vertical connections; this methodology is effective even when cycle constraints are present. Chameleon has produced optimal results on a wide range of industrial and academic examples for a variety of layer and pitch combinations, and can handle a variety of technology constraints.> Douglas Braun, Jeffrey L. Burns, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli, Kartikeya Mayaram, Srini Devadas, Hi-Keung Tony Ma |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 3 |
| 1987 | A Parallel Simulated Annealing Algorithm for the Placement of Macro-CellsabstractA modification of the classical Simulated Annealing algorithm for the macro-cell placement problem is proposed for implementation on multiprocessor systems. The algorithm has been implemented on the Sequent Balance 8000, a multiprocessor system with a shared-memory architecture. Experimental results show that the new algorithm obtains results comparable in quality to those of the single processor version; processor utilization is greater than 80 percent using up to eight processors. Andrea Casotto, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 1986 | Chameleon: a new multi-layer channel routerabstractNew techniques for routing general multi-layer channels are introduced. These techniques can handle a variety of technology constraints. For example, linewidth and line-to-line spacing can be specified independently for each layer, and contact stacking can be allowed or forbidden. These techniques have been implemented in a new multi-layer channel router called Chameleon. Chameleon consists of two stages: a partitioner and a detailed router. The partitioner divides the problem into two and three-layer subproblems such that global channel area is minimized. The detailed router then implements the connections using generalizations of the algorithms used in YACR2. In particular a three-dimensional maze router is used which guarantees that any problem can be routed even when cyclic constraints are present. Chameleon produces optimal results on a wide range of industrial and academic examples for any number of layers and pitch combinations. Douglas Braun, Jeffrey L. Burns, Srini Devadas, Hi-Keung Tony Ma, Kartikeya Mayaram, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli |
DAC | 6 |