The paper presents a novel method for size reduction of a signature-based diagnostic dictionary that is used in testing of static and delay faults in connections by means of specific Interconnect BIST (IBIST) structure. The IBIST has a form of a ring register R-LFSR which feedback lines constitute connections under test. The previous studies of the authors assumed implementation of a single 2n-bit R-LFSR structure for testing and diagnosis of faults occurring in buses with the width n ≤ 32 bits. As size of the diagnostic dictionary rapidly grows in pace with both the number of connections under test and increase of the fault-multiplicity, it was a significant drawback that hindered examination of very wide buses. This study proposes how to solve this problem by splitting the n-bit bus into b fragments with the width of k bits each. Every fragment is tested by an independent R-LFSR register with its length of 2k bits. The study assumes faults with the maximum fault-multiplicity rmax=3 for each k-bit fragment of the bus, where the faults present combinations of stuck-at 0/1, AND /OR shorts of two or three lines and delay faults. The proposed approach has made it possible to significantly reduce size of the signature-based diagnostic dictionary that is necessary to locate and identify the mentioned faults. It was achieved by substantial reduction of the number of signature entries covered by the dictionary as well as by shortening the length of the signatures by b times. Moreover, the newly developed method enables to locate and identify substantial part of faults for the entire bus with the width of n, where the multiplicity of faults can be even as high as b rmax.

The paper is devoted to a test-per-clock method of an at-speed testing of crosstalk faults in long interconnects between cores in systems-on-a-Chip. A linear feedback shift register (LFSR) composed of 2n flip-flops and implementing primitive polynomial was used as a test pattern generator (TPG) for an interconnect network comprised of n nets. In our approach every second output of the LFSR is connected to the interconnect network under test (INUT). Simulation-based experiments were carried out to verify effectiveness of vector sequences produced by the proposed TPG in detection of crosstalk faults provoked at victim net by simultaneous occurrence of rising (falling) edges 01(10) at k aggressor lines. Crosstalk faults causing occurrence of a positive (negative) glitch at a victim line having constant value 00(11) as well as the ones that make the edge delayed with an opposite direction 10(01) at a victim line were taken into consideration. Experimental results demonstrated that for n e {8,12,16,20,24,28,32} and k<

The paper introduces a novel idea of interconnect fault detection, localization and identification based on test response compaction. The above-mentioned operations are made at-speed. The testing process has been split into two steps. The first one is the detection step using a short test sequence of little diagnostic resolution. The second step is the localization step by means of a long, full diagnostic resolution sequence and it is made only in the case of the detection of faults in the first step. The final fault identification phase exploits information stored in the signatures. Because the signature is chosen to be 32 bit long aliasing is negligible. The proposed hardware concept is independent of the type of both the detection test sequence and the localization test sequence. The theory given in the paper is illustrated by the simulation results. Moreover the paper proposes to test testing hardware itself what makes the results reliable

The paper proposes the approach of designing CA registers that work as quick pattern generators. A new effective method of setting the initial state of such registers is presented. It is based on switching a n-cell CA register into a concatenation of p CdSR registers (Cellular Automata quasi Shift Register) each containing r cells and connected with characteristic polynomial x'. The resultant characteristic polynomial of such concatenation is p(x)=x/sup n/. Such concatenation of p registers CASR is referred as PCASR. The paper proves the possibility of setting a PCASR to any initial state by n-bit input sequence without the need of switching flip-flops into the D flip-flop mode. Moreover, it has been proven that any input sequence would be repeated at the output of a n-cell PCASR after n-clock cycle delay. Finally an effective procedure of testing PCASR is proposed.

An application of new idea of designing circular self-test path (CSTP) for EDAC circuit is given in the paper. The new BIST scheme called in the paper as a condensed circular self-test path (CCSTP=C/sup 2/STP) makes possible to reduce significantly the number of CBIST cells to a smaller value. We focus on the analysis of the state transition graph (STG) as a key to understand the state coverage, fault coverage, and zero aliasing of condensed circular BIST (CBIST) schemes. There are given two examples of C/sup 2/BIST design. Particularly, the simple example of C/sup 2/STP design for 4-bit errors detection and errors correction (EDAC) circuit indicates advantages of such BIST technique. On the basis of this example it is shown that the time and complexity of simulation process for C/sup 2/STP is smaller than those for CSTP configuration and the seek time of a solution giving quasi optimal effectiveness for C/sup 2/STP is considerably shorter.

In this paper for an arbitrary linear separable code the concept of a COde Preserving Multi-Input Signature Register COPMISR is introduced. For a code with k control bits 2/sup k2/ different COPMISR's can be designed. The optimum COPMISR with a minimum number of XOR-gates can be chosen from this large set. By different examples it is shown how the newly introduced COPMISR can be simultaneously utilized for concurrent checking, testing and localization of an eventually erroneous component of the monitored system. Since parity codes, group-parity codes, duplication codes and Hamming codes are special linear separable codes the concept of the COPMISR has a wide range of applications in different areas of on-line error detection and BIST.

A bottom-top exclusive OR (BTE) type multiple input linear feedback shift register (MISR) and a top-bottom exclusive OR (TBE) type MISR which use only (t+1)/2 XOR gates in their linear feedback are presented. An algebraic analysis of the operation and certain analytical results regarding the detection capability of a BTE MISR are included. Infirmities of certain BTE type MISRs and TBE type MISRs with a reducible characteristic polynomial have been made. The proof that the probability of error sequence aliasing on a single input of BTE or TBE type MISR, where a characteristic polynomial of degree n is reducible, asymptotically approaches a value greater or equal to 2/sup -n/ is also given.>

In this paper drawbacks of the three-state data compressor in the form of the unit decoder 3/2—JK flip-flop are described. The main results of the paper are the algebraic operation model and the description of detection capability of a new three-state data stream compressor consisting of decoder 3/2 and a two-input shift register TISR. In particular, the properties of the unit decoder 3/2—TISR in detecting faults of the s-a-0, s- a-1, and s-a-HZ type are discussed. In this paper important aspects of the application of the new compressor are given. An example of the new compressor's performance scheme is also described. An additional result of this paper is the description of the operation model and the detection capability of the multiinput shift register MISR in which the most significant bit and other selected flip-flop output signals are fed back to the least significant bit positions via Exclusive-OR gates outside the flip-flops.

The following comments on the paper1by M. A. Breuer may be in order.