In a DMT (discrete multitone) system, when the sampling rate is raised to increase the data transmission rate, the sub-channel spacing grows with the same ratio if the identical FFT is used. The sub-channel flatness and capacity for VDSL test loops are calculated, and the performance of various symbol rates, from 4 kHz to 20 kHz, are also analyzed to find the optimal solution of a DMT VDSL system.

In this paper, we propose a pilot channel aided adaptable interference cancellation (IC) scheme which combines serial (SIC) and parallel (PIC) interference cancellation to adapt to different services under different circumstances for uplink wideband DS/CDMA systems. The processing delay and computational complexity can be adjusted based on system loading and required performance. The interference between data channel signals and pilot channel signals under multipath fading are also taken into consideration. This results in better quality both on channel parameter estimation and user data detection. Compared with SIC and PIC, the proposed scheme shows better performance with reasonable hardware while it needs shorter processing delay than SIC.

A guard-interval based symbol and frequency synchronization technique with an extended observation interval of the OFDM transmission with higher level modulations is investigated for the wireless radio environments. The performance of the proposed guard-interval based symbol and frequency synchronization is evaluated by the computer simulations.

An asynchronous symbol timing recovery with adaptive interpolation filter is investigated for high data-rate digital mobile radio. The timing error estimation employing a general type of nonlinearity is used to estimate the timing error by the discrete-time spectral method. An adaptive interpolation filter is adopted to mitigate both the timing error and inter-symbol interference (ISI) due to multipath fading. Computer simulations are employed to evaluate the performance of the symbol timing recovery over the environment with additive white Gaussian noise (AWGN), carrier frequency offset and Rayleigh fading. The proposed timing synchronizer is well suited to burst mode, narrow-band, high data-rate digital mobile radio.

Coherent uplink detection of an asynchronous CDMA terrestrial radio system is feasible with a pilot-assisted channel estimation. In this paper, we present an interpolated M-slot averaging scheme for pilot-symbol assisted channel estimation. The M-slot averaging samples are input to a Lagrange interpolator to obtain the desired channel estimates. The hardware of this new scheme is simpler than the modified weighted multi-slot averaging (WMSA) estimation filter with comparable tracking ability.

The hardware implementation issues for an adaptive multialphabet arithmetic coder are discussed. A simple weighted history model is proposed to encode the video data. This model uses a weighted finite buffer to model the cumulative density function of the arithmetic coder. The performance of the weighted history model is evaluated together with several other well-known models. To access, search, and update the cumulative frequencies corresponding to model symbols in real time, we present a low complexity multibase cumulative occurrence array structure that can offer the probability information for high-speed encoding and decoding. For the application in video compression, the multialphabet arithmetic coding with weighted history model can be a good choice as the variable length coding of the video symbols.

This paper derives a frequency acquisition algorithm for orthogonal frequency division multiplexing (OFDM) systems. This frequency acquisition algorithm is a modification of the frequency tracking algorithm introduced by Moose (see IEEE Trans. Commun., vol.42, no.10, p.2908-14, 1994), which uses a repeated data symbol and a maximum likelihood estimation (MLE) algorithm to estimate the frequency offset. The estimate is extremely accurate but the acquisition range is limited to /spl plusmn/1/2 of the intercarrier spacing. With some modifications of the frequency tracking scheme and an assumption of a multipath channel, the frequency acquisition can be converted to an analogous PN sequence acquisition problem. Therefore, a partial-sum correlator with an appropriate threshold can be used to acquire the frequency offset.

A minimum mean-squared error (MMSE) linear correlation receiver has been presented to efficiently suppress multiple access interference (MAI) for direct-sequence code-division multiple-access (DS/CDMA) systems in Gaussian channels. The MMSE linear receiver is near-far resistant so as to reduce the requirement of perfect power control. However, additive non-Gaussian impulsive noise bursts in the realistic communication channels. In this paper, we analyze the performance of a linear correlation receiver operating in the presence of MAI and the ambient noise modeled as a symmetric stable process. We also use the Fourier-Bessel series expansion to approximate the exact form of performance analysis. The learning curves of an adaptive linear correlation receiver with different training methods are then examined by computer simulations.

A class of four-level periodic sequences derived from the binary m-sequences are presented. These sequences can be used as the training sequences in adaptive channel estimation and equalization with fast start-up for multilevel PAM or QAM transmission. The sequence generator can be implemented by simple hardware.

The use of square-root recursive prediction error (RPE) algorithm for multi-layer perceptron (MLP) based decision feedback equalization (DFE) over frequency selective fading channel is presented in this paper. Computer simulation demonstrates that considerable bit error rate (BER) improvement relative to the square-root Kalman can be achieved by using the proposed scheme.

In high density digital magnetic recording system, it is found from experimental results that the peak position of transition pulse is shifted by the effect of the adjacent transitions. The nonlinear intersymbol interference (ISI) induced by the nonlinear pulse shift can be equalized by employing a Volterra-DFE, in which a Volterra filter is used in the feedback section of decision feedback structure. The timing function, in conjunction with the channel estimator, is used to control the sampling clock to maximize the signal-to-noise ratio at the output of Volterra-DFE. Computer simulation show that the Volterra-DFE outperforms the conventional DFE in both output SNR and BER.>

It has been shown previously that the multiple trellis coded modulation (MTCM) can perform better than the conventional TCM over fading channels and AWGN channels, at the cost of additional computations per trellis branch. Two methods for decomposing the MTCM are studied. The first method is the direct decomposition method, which can reduce the decoder complexity without sacrificing the BER performance. For those codes that can not be decomposed with such method, a bit-neglection method is developed. This method can also reduce the decoder complexity but with severe degradation in BER performance. Multiprocessing is then accommodated to circumvent the degradation. A new metric with variable parameter for sequential decoding over the fading channels is derived. Computer simulations are used to aid the studies of the relations between the performances, the variable parameter, and the multiprocessing scheme.>

A high speed decoding algorithm using a modified step-by-step method for t-error-correcting Reed-Solomon codes is introduced. Based on this algorithm, a sequential decoder and a vector decoder are then proposed. These two decoders can be constructed by four basic modules: the syndrome calculation module, the comparison module, the decision module, and the shift-control module. These decoders can be applied for both binary and nonbinary data transmissions working at high data rate. Because of the simplicity in structure and circuit realization, a decoder employing this algorithm can be easily implemented in a monolithic chip by the VLSI technology.>

A high-speed real-time decoder for t-error-correcting binary BCH codes based on a modified step-by-step decoding algorithm is presented. The average operation cycle, for decoding each received word is just equal to the block length of the codeword. The decoder is constructed of three modules: the syndrome module, the comparison module, and the error corrector. Since all of the modules can be implemented by systolic circuits, the data rate of this decoder can theoretically be up to the rate of the inverse of two logic-gate delays operating from approximately several hundreds of megabits per second to the order of gigabits per second. Thus, the decoder can be applied in broadband service and video processing. By avoiding inverse operations in the step-by-step decoding method, the circuit complexity of the decoder can be made much less than that of the standard algebraic method. The detailed circuit diagrams of the comparison module and error corrector for double- and triple-error-correcting binary BCH codes are given for illustration.>

An algebraic decoding method for triple-error-correcting binary BCH codes applicable to complete decoding of the (23,12,7) Golay code has been proved by M. Elia (see ibid., vol.IT-33, p.150-1, 1987). A modified step-by-step complete decoding algorithm of this Golay code is introduced which needs fewer shift operations than Kasami's error-trapping decoder. Based on the algorithm, a high-speed hardware decoder of this code is proposed.>

To apply multiple-valued logic (MVL) to digital filter design, a novel structure of digital filter, named signed binary delta modulation digital filter (SBDM-DF), is presented. The SBDM-DF uses a tristate quantizer allowing (1, 0, -1) states to encode the input signal. Signed binary number representation is used for filter coefficients in order to attain carrier-free addition with signed binary adder tree (SBAT). In hardware realization, ternary logic circuits can be adopted to increase the carried information per wire. From the analysis of SNR (signal-to-noise-ratio) characteristics of SBDM and conventional delta modulation (DM), it is found that the sampling frequency of SBDM can be reduced by at least one-half, relative to DM, for the same signal quality. The design procedure of SBDM-DF is illustrated by a typical low-pass filter using the Kaiser-windowing technique.>

Bit-level systolic architectures based on an inner-product computation scheme for finite-impulse response (FIR) and infinite-impulse-response (IIR) digital are presented. The FIR filter structure is optimized in the sense that for a given clock rate, both the utilization efficiency and average throughput are maximized. The IIR filter structure has approximately the same utilization efficiency and throughput rate as previous related techniques for processing a single data stream (channel), but it allows two data streams to be processed concurrently to double the performance. This feature makes the IIR system attractive for use in applications where multiple filtering and particularly bandpass analysis are required.>