Iterative division algorithms based on multiplication are popular because they are fast and may utilize an already existing hardware multiplier. Two popular methods based on multiplication are Newton-Raphson and Goldschmidt's algorithm. To achieve concurrent error correction, Time Shared Triple Modular Redundancy (TSTMR) may be applied to both kinds of dividers. The hardware multiplier is divided into thirds, and the rest of the divider logic replicated around each part, to provide three independent dividers. While this reduces the size of the fault-tolerant dividers over that of traditional TMR, latency may be increased. However, both division algorithms can be modified to use lower precision multiplications during the early iterations. This saves multiply cycles and, hence, produces a faster divider.

Executing multiple threads simultaneously on superscalar processor can improve hardware resource utilization and instruction throughput. The Multi-Threaded Superscalar (MTS) processor efficiently achieves the concurrent execution of multiple instruction streams using a VLIW, multiple functional unit architecture. However, the limitations of the memory system may impede the potential performance of the MTS processor. An interactive, parameter-driven simulator of the MTS architecture was developed using SES/workbench. A set of numerical benchmarks was run on it with varying memory system configurations. Assuming a single instruction cache, a single data cache, and one instruction queue per thread, varied parameters included the size of the instruction queues, the number of ports to the instruction cache, main memory latency, and cache hit rates. Based on simulation results, optimal values were chosen for certain parameters. To reasonably utilize the MTS processor, the memory system must provide at least 64 instruction bytes per cycle, though the demands for data access are far less severe. For reasonable memory speeds, this requires a roughly IMB three-ported instruction cache capable of providing 128 bits per port per cycle, as well as an IMB single-ported 32-bit wide data cache. A more realistic multilevel cache hierarchy is proposed.