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M. Grinchuk

dblp:49/454 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2007
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test		 0.112007
Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2007
Electronic design automation › hardware verification and test › design for testability
scan-based testing		 0.112007
Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2007
Electronic design automation › hardware verification and test
test application time reduction		 0.112007
Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2007
Electronic design automation › hardware verification and test
test data compression		 0.112007
Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2007
Electronic design automation › hardware verification and test › low-power testing
test power reduction		 0.112007
Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2007

Methods — techniques the papers use, named apart from their topics

systematic scan reconfiguration · 0.1segmented addressable scan · 0.1
YearPublicationVenuePosition
2007 Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration
abstract
This paper presents segmented addressable scan (SAS), a test architecture that addresses test data volume, test application time, test power consumption, and tester channel requirements using a hardware overhead of a few gates per scan chain. Using SAS, this paper also presents systematic scan reconfiguration, a test data compression algorithm that is applied to achieve 10× to 40× compression ratios without requiring any information from the automatic-test-pattern-generation tool about the unspecified bits. The architecture and the algorithm were applied to both single stuck as well as transition fault test sets.
Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Erik Chmelar, M. Grinchuk, Arun Gunda
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.4