It is expected that a highly-safe intelligent system which makes risk avoidance in the real-world environment where human lives. In order to detect dangerous situations, it is indispensable to accurately recognize risk events from the input image information, i.e., high-accuracy scene recognition. In this paper, it is clarified that the high-accuracy scene recognition can be achieved by combination of the convolution neural network which extracts the feature of an input image and the support vector machine for classification. In the scene recognition of a single danger event, it is not possible to recognize multiple event occurrences (multi-class classification). We propose a method to realize multi-class classification without decreasing the recognition accuracy by selectively using an individual classifier generated for each event.

Live-feeling communication is a seamless process of intelligent system estimating user intention solely on passive user-to-robot communication of user emotions and body movements. In this paper we study the live-feeling communication in an entertainment framework; a real-time streaming event (football) is split into set of important and relevant scenes, and for each scene the user intention is estimated. For each scene the amount of desired details and the desired content is estimated. In order to obtain the best possible estimation result we predict the user intention for each scene using a set of different predictors by using a parameter search approach. We show that using the collected data certain situations can be estimated with accuracy of up to 95% while others are still beyond the reach of the used prediction algorithms.

This paper presents a high-throughput and ultralow-power asynchronous domino logic pipeline design method, targeting to latch-free and extremely fine-grain OR gate-level design. The data paths are composed of a mixture of dual-rail and single-rail domino gates. Dual-rail domino gates are limited to construct a stable critical data path. Based on this critical data path, the handshake circuits are greatly simplified, which offers the pipeline high throughput as well as low power consumption. Moreover, the stable critical data path enables the adoption of single-rail domino gates in the noncritical data paths. This further saves a lot of power by reducing the overhead of logic circuits. An 8×8 array style multiplier is used for evaluating the proposed pipeline method. Compared with a bundled-data asynchronous domino logic pipeline, the proposed pipeline, respectively, saves up to 60.2% and 24.5% of energy in the best case and the worst case when processing different data patterns.

In this paper we present improvements to the cost of quantum circuits implemented with 2n-lines circuit implementation. The 2n-line circuit implementation is intended for the linear nearest neighbor quantum circuits and implements any quantum circuits in such manner that they can be directly mapped to quantum implementations. In this paper we propose a replacement strategy for 2- and 3-qubit patterns detected on the control lines. It is demonstrated that application of this strategy leads to a considerable reduction of circuit cost.

Heterogeneous multi-core architecture with CPUs and accelerators attract many attentions since they can achieve power-efficient computing in various areas from low-power embedded processing to high-performance computing. Since the optimal architecture is different from application to applications, it is important to explore suitable architectures for different applications. In this paper, we propose an FPGA-based heterogeneous multi-core platform with custom accelerators for power-efficient computing. Our platform allows to select the most suitable accelerator according to the requirements of an application. Moreover, we optimize the number of ALUs, memory and interconnection network of the selected accelerators to increase the performance and to reduce the power consumption. Experimental results with simple media processing applications times power-efficient compared to the GPU.

This paper presents a fine-grain pipelined asynchronous circuit that uses a mixture of dual-rail and single-rail logic. Dual-rail logic is limited to construct a stable critical path. Based on this critical path, the handshake control circuit is greatly simplified, which improves the performance of speed and power consumption. On the other hand, non-critical paths are composed of single-rail logic which has small logic overhead and the entire pipelined circuit has no intermediate registers or latches. To evaluate the proposed design method, an array style multiplier is designed and simulated in a 65nm design rule. The multiplier works as high as 4.35G data-set/s. Compared to the classical synchronous circuit, the proposed circuit has no active power consumption when there are no data operation. Even the circuits work at peak speed, the proposed circuit still reduces the power consumption by 35%.

This paper presents an asynchronous FPGA that combines four-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. Four-phase dual-rail encoding is used for small area and low power of function units, while LEDR encoding for high throughput and low power of data transfer. The proposed FPGA is fabricated in the e-Shuttle 65nm CMOS process and operates at 870 MHz. Compared to the synchronous FPGA, the power consumption is reduced by 38% for the workload of 15%.

The simple and cheap memory-less RFID tag systems have found many diverse applications. The available singulation algorithms for such systems adopt either single-slot or multi-slot frames with a fixed frame size, independent of tag population. A single-slot scheme has good performance in terms of the number of overall slots N, but it can cause a very large number of requests R. A multi-slot scheme, on the other hand, achieves good performance of R, but it may introduce an unacceptable large N. In this paper, we propose an adaptive frame size singulation scheme for memory-less RFID systems. Our basic idea is to adaptively choose a suitable frame size based on tag population information collected during the singulation, such that the number of unnecessary collision and idle slots can be reduced. Analytical models are also derived for the performance analysis of the new scheme. Surprisingly, our theoretical and simulation studies indicated that through adopting such adaptive frame size, the new singulation scheme can achieve a performance of N as good as the single-slot scheme, and at same time, guarantees a performance of R similar to the available multi-slot schemes.

The simple and cheap passive RFID tag systems have recently been used for efficient localization of indoor mobile robots, where each RFID tag stores its own absolute position and the mobile robot carrying an RFID reader scans the RFID tags to localize itself. The available localization schemes using passive RFID systems do not consider the scanning delay which may cause location estimation error especially when the robot moves with a high speed. In this paper, a new Non-Blocking scanning (reading) scheme is proposed to avoid collisions such that the scanning delay and consequently the localization error can be reduced. This scheme avoids collision among tags replies by assigning tags IDs based on the FCA coloring scheme. Theoretical and simulation studies indicate that the new Non-Blocking scheme combined with the new tag arrangement pattern can achieve a good RFID localization performance in terms of both estimation error and scanning delay.

High performance and low-power very large-scale integrations are required to implement complex media processing applications on mobile devices. Heterogeneous multicore processors are a promising way to achieve this objective. They contain multiple accelerator cores and CPU cores to increase the processing speed. Since media processing applications access a huge amount of data, fast address generation is very important. To increase the address generation speed, accelerator cores contain address generation units (AGUs). To reduce the power consumption, the AGUs have limited hardware resources such as adders and counters. Therefore, the AGUs generate simple addressing patterns where the address increases linearly in each clock cycle. Media processing applications frequently encounter addressing patterns where the same data are accessed in different time slots. To implement such addressing patterns, the same data have to be allocated into multiple memory addresses in such a way that those addresses can be generated by the AGUs. Allocation of the same data in multiple addresses is called the “data-duplication.” The data-duplication increases the data-transfer time and also the total processing time significantly. To remove such data-transfer bottlenecks, this paper proposes a memory allocation method that exploits the temporal and spatial locality of the memory access in media processing applications. We evaluate the proposed method using media processing applications to validate its effectiveness. According to the results, the proposed method reduces the total processing time by 14% to more than 85% compared to previous works.

This paper presents a field-programmable gate array (FPGA) based on lookup table level fine-grain power gating with small overheads. The power gating technique implemented in the proposed architecture can directly detect the activity of each look-up-table easily by exploiting features of asynchronous architectures. Moreover, detecting the data arrival in advance prevents the delay increase for waking-up and the power consumption of unnecessary power switching. Since the power gating technique has small overheads, the granularity size of a power-gated domain is as fine as a single two-input and one-output lookup table. The proposed FPGA is fabricated using the ASPLA 90-nm CMOS process with dual threshold voltages. We use an image processing application called “template matching” for evaluation. Since the proposed FPGA is suitable for processing where the workload changes dynamically, an adaptive algorithm where a small computational kernel is employed. Compared to a synchronous FPGA and an asynchronous FPGA without power gating, the power consumption is reduced respectively by 38% and 15% at 85°C.

It has been experimentally proven that realizing universal quantum gates using higher-radices logic is practically and technologically possible. We developed a Parallel Genetic Algorithm that synthesizes Boolean reversible circuits realized with a variety of quantum gates on qudits with various radices. We describe the experiments that we conducted using GPU programming. Various approaches to fitness function formulation were applied to obtain various realizations of well known universal Boolean reversible quantum gates.

This is the first implementation of an FPGA based on autonomous fine-grain power-gating. To cut the power consumption of clock network and detect the activity of the cell efficiently, asynchronous architecture is full exploited. The proposed FPGA is fabricated in a 90nm CMOS process with dual threshold voltages. It is more efficient in power than the synchronous FPGA at less than 30% utilization.

One major issue in designing image processors is to design a memory system that supports parallel access with a simple interconnection network. This paper presents an efficient memory allocation to minimize the number of memory modules and processing elements with a parallel access capability when multiple windows with arbitrary shapes are specified. This paper also presents an efficient search method based on regularity of window-type image processing. We give some practical examples including a stereo-matching processor for acquiring 3-D information, and an optical-flow processor for motion estimation. These examples show that the numbers of memory modules are reduced to 2.7% and 10%, respectively, in comparison with a basic approach. It is also shown that the search time is less than 1 ms for practical image sizes and window sizes.

This paper presents a vehicle detection algorithm using 3-dimensional(3D) information and its FPGA implementation. For high-speed acquisition of 3D information, feature- based stereo matching is employed to reduce search area. Our algorithm consists of some tasks with high degree of column- level parallelism. Based on the parallelism, we propose area- efficient VLSI architecture with local data transfer between memory modules and processing elements. Images are equally divided into blocks with some columns, and a block is allocated to a PE. Each PE performs the processing in parallel. The proposed architecture is implemented on FPGA (Altera Stratix EP1S40F1020C7). For specifications of image size 640 times 480, 100 frames/sec, and operating frequency 100 MHz, only 11,000 logic elements (< 30%) are required for 30 PEs.

Multi-context FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant overhead in area and power consumption. This paper presents two key technologies. The first is a floating-gate-MOS functional pass gate that merges storage and switching functions area - efficiently. The second is the use of a hybrid multiple-valued/binary context switching signal that eliminates redundancy of a conventional multi-context (MC) switch with high scalability. The transistor count of the proposed MC-switch is reduced to 7% in comparison with that of a SRAM-based one.

This paper presents an efficient search method for a scheduling and module selection problem using multiple supply voltages so as to minimize dynamic energy consumption under time and area constraints. The proposed algorithm is based on a genetic algorithm so that it can find near-optimal solutions in a short time for large-size problems, n efficient search can be achieved by crossover that prevents generating nonvalid individuals and a local search is also utilized in the algorithm. Experimental results for large-size problems with 1,000 operations demonstrate that the proposed method can achieve significant energy reduction up to 50 percent and can find a near-optimal solution (within 2.8 percent from the lower bound of optimal solutions) in 10 minutes. On the other hand, the ILP-based method cannot find any feasible solution in one hour for the large-size problem, even if a state-of-art mathematical programming solver is used.

Stereo vision is a well known method to acquire 3D information. One important problem in stereo vision is to establish reliable correspondence between images. Another problem is that the correspondence search is time-consuming. This paper presents a reliable stereo-matching algorithm and a new parallel VLSI processor architecture for stereo matching. One commonly-used method to establish correspondence between images is the SAD (sum of absolute differences) method. A window size is iteratively enlarged to select as small a window for each pixel as possible that can avoid ambiguity based on uniqueness of a minimum of an SAD graph. This process is called a global search. Next, the estimate of the corresponding pixel obtained by the global search is iteratively refined by shrinking the window size. To avoid ambiguity with a small window size, the correspondence estimate obtained by the global search is efficiently used. The proposed algorithm has regular data flow based on iterations of SAD computation so that it is suitable for parallel processing.

A new multiple-valued current-mode (MVCM) integrated circuit based on dual-rail differential logic, whose current-driving capability is high at a low supply voltage, is proposed to realize a totally self-checking circuit and an asynchronous-control circuit. Two nMOS transistors with different threshold voltages are used as complementary pass switches in the proposed differential-pair circuit (DPC), so that the outputs of the DPC always become stable even when non-code-word input (1, 1) are applied, which makes it possible to design a self-checking circuit by using the MVCM circuit. In addition, the dual-rail MVCM circuit technique can be naturally utilized for efficient realization of a two-color dual-rail data-transfer scheme in asynchronous communication. In fact, it is demonstrated that the performance of both a self-checking multiplier and a simple asynchronous control circuit is superior to that of the corresponding ordinary implementation.

This paper presents the design of a new high-performance VLSI processor based on a systematic methodology for area minimization under a time constraint. A VLSI-oriented algorithm based on regular iterations of coordinate transformation and matching operation are introduced. The VLSI-processor consists of several identical clusters which has a CAM for parallel matching operation and PEs for parallel coordinate transformation. Under a condition of 100% utilization of PEs and a CAM, area minimization of the VLSI-processor is attributed to minimization of area-time products of a CAM and a PE. A multiport CAM (MCAM) and a PE based on bit-serial pipelined architecture can be efficiently employed for the minimization. The result shows that the total area can be reduced by about 30% in comparison with a straightforward design and that the performance is several ten thousand times higher than that of a general-purpose processor.

A new current-source control technique is proposed to design a low-power high-speed multiple-valued current-mode (MVCM) integrated circuit in a low supply voltage. The use of a differential logic circuit (DLC) with a pair of dual-rail inputs makes the input voltage swing small, which results in a high driving capability at a lower supply voltage, while having large static power dissipation. In the proposed DLC using switched current control, the static power dissipation is greatly reduced because current sources in non-active circuit blocks are switched off. In the current control, no additional transistors are required to control the current sources because a current-control circuit is already used in the threshold detector. As a typical example of arithmetic circuits, a new 1.5 V-supply 54/spl times/54-bit multiplier based on a 0.8 /spl mu/m standard CMOS technology is also designed. Its performance is about 1.3 times faster than that of a binary fastest multiplier under the normalized power dissipation.

Presents a very-large-scale-integration (VLSI)-oriented high-speed multiplier design method based on carry-propagation-free addition trees and a circuit technique, so-called multiple-valued current-mode (MVCM) circuits. The carry-propagation-free addition method uses a redundant digit set such as /spl lcub/0,1,2,3/spl rcub/ and /spl lcub/0,1,2,3,4/spl rcub/. The number representations using such redundant digit sets are called redundant positive-digit number representations. The carry-propagation-free addition is written by three steps, and the adder can be designed directly and efficiently from the algorithm using MVCM circuits. The designed multiplier internally using the MVCM parallel adder with the digit set /spl lcub/0,1,2,3/spl rcub/ in radix 2 has attractive features on speed, regularity of the structure, and reduced complexities of active elements and interconnections. A prototype CMOS integrated circuit of the MVCM parallel adder has been implemented, and its stable operation has been confirmed. Other possible schemes of multipliers with redundant digit sets using MVCM technology are discussed.>

A VLSI-oriented matrix multiply-addition processor (MMP) is proposed for minimum-delay-time inverse dynamics computation on a linear array structure. It is shown that the delay time of the inverse dynamics computation becomes minimum based on the concept of the odd-even alternative computation. The MMP architecture is systematically designed by using two types of data-dependence graphs of the odd-even alternative computation. It is demonstrated by the layout evaluation that the MMP can be easily implemented in a single chip using the current VLSI technology (e.g. 1 mu m CMOS). The performance with regard to the delay time is higher than for previously reported architectures.>

The authors present an LSI (large-scale integrated) circuit for high-speed inverse kinematics computation. They demonstrate that inverse kinematic solutions can be described by two-dimensional vector rotations and arc tangent operations and that these operations can be efficiently computed by the coordinate rotation digital computer (CORDIC) algorithms. The chip is fabricated using 1.5- mu m CMOS gate array technology, and the design of the arithmetic unit on the chip is based on the CORDIC algorithms. Pipelining is fully used in the processor to enhance the operating ration up to 100%. The resulting compact inverse kinematics processor is composed of the above chip and a few memory chips for program and data. The processor can be used for various kinds of manipulators.>

The ternary T-gate can be used as a basic building block to construct both combinational and sequential circuits. Since the T-gate is one kind of tree-type universal logic module, any combinational circuit can be built up with modular logic arrays. For constructing ternary memory elements, however, the T-gate is required to be static hazard-free. A theoretical study is done on the necessary conditions for the practical realization of the static-hazard-free T-gate. On the basis of the result obtained, the static-hazard-free T-gate is realized using the ECL technique. The static-hazard-free T-gates obtained here can be used as building blocks to construct memory elements. Various memory elements such as D flip-flap-flop (FFF), D master-slave FFF, B master-slave FFF, and counting FFF is constructed easily. Using these memory elements, three different types of ternary counters can be designed and realized. They are an asynchronous signed ternary counter, a synchronous signed ternary counter, and a counter based on a shift register. Their design methods are discussed. These ternary counters are superior to the binary ones in that the up-down cotnting can easily be carried out by one input signal.

This correspondence presents a theoretical study on the synthesis of multiple-valued logic networks based on tree-type universal logic modules (T-ULM's). The mathematical notation of T-ULM is introduced. On the basis of the mathematical properties, an algorithm for synthesizing an arbitrary logic function of n variables with a smaller number of modules is presented. In this algorithm, only true and constant inputs are allowed at input terminals. The algorithm consists of two parts. The first one is a functional decomposition, and the other one is the proper order of the expansion which is the problem of zinding the most incomplete tree structure. Thus it is established that the systematic and nonexhaustive procedure of the algorithm gives a suboptimal solution for the reduction of the number of T-ULM's.