Digital computing-in-memory (DCIM) systems integrate complex digital logic with parasitic-sensitive bitcell arrays, presenting unique physical design challenges. Conventional design strategies often fall short in these systems due to irregular dataflow patterns and excessive interconnect lengths, which degrade performance and increase parasitic effects. As a result, current DCIM implementations frequently rely on manual layout, which is both time-consuming and a major bottleneck in the design cycle. While existing DCIM layout synthesis frameworks attempt to automate this process using template-based placement methods inspired by manual design, their rigid constraints can lead to inefficient area utilization and increased core sizes. To address these limitations, we propose DAMIL-DCIM+, a novel placement framework that combines the structural clarity of template-based methods with the flexibility of optimization-based techniques. Specifically, DAMIL-DCIM+ employs a global dataflow-aware floorplan to guide placement and leverages MILP-based detailed placement to optimize wirelength and preserve dataflow regularity. Inspired by self-assembling design principles, this approach enables scalable and structured integration of parasitic-sensitive components. The hybrid methodology of DAMIL-DCIM+ reduces total wirelength, lowers parasitic effects, and enhances performance while maintaining design regularity. Experimental results on a 28nm DCIM circuit demonstrate that DAMIL-DCIM+ improves operating frequency by 25.2% and reduces power consumption by 19.6% compared to Cadence Innovus, without increasing core area.

The design and verification process for analog circuits can be long and tedious, wherein designers rely heavily on manual effort to create circuits and draw layouts, thereby limiting turn-around-time and design scale and increasing costs. Various previous works have tried to solve this issue by leveraging digital automated place-and-route (APR) tools, but they involve replacing analog elements with digital counterparts, thereby dampening performance. In this work, we propose a digital flow-based approach to design all-analog circuits that dramatically speeds up the design and layout process while retaining the benefits of true analog topologies and demonstrate the performance for three low-dropout regulators (LDOs). Fabricated in 65-nm CMOS, measurement results show that the generated LDOs achieve up to 99.95% peak current efficiency, a figure-of-merit (FOM) of 4.6 ps, and up to 63.93% reduction in input offset variability with respect to their manually designed counterparts.

This paper presents an ultra-low power (ULP) node-controlling system-on-chip (SoC) used for power-mode management and phantom energy reduction of miscellaneous electric loads (MELs). The SoC is powered from a single 2.5 V voltage supply enabled by the integrated power management unit (PMU) and can control up to 16 MELs due to the on-chip 16-channel correlator and the 32b RISC-V microprocessor. To further reduce the system power consumption, two clock domains have been adopted for the correlator and the processor separately. Fabricated in 65-nm CMOS, the measured minimum power consumption of the proposed SoC is only 85 nW at 0.45 V voltage supply and 1 kHz clock frequency. The measured maximum operating frequency can go up to 148 kHz with a 0.55 V supply. An application experiment successfully demonstrates that the SoC controls the power modes of MELs from wake-up to cut-off to save the average power and phantom energy.