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Chiunn-Shyong Ye

dblp:49/5989 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1984
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%
Theoretical computer science
1 paper
Coding theory · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
digital circuit design
0.011984
The VLSI Implementation of a Reed-Solomon Encoder Using Berlekamp's Bit-Serial Multiplier Algorithm · IEEE Trans. Computers 1984
Coding theory › error-correcting codes
reed-solomon codes
0.011984
The VLSI Implementation of a Reed-Solomon Encoder Using Berlekamp's Bit-Serial Multiplier Algorithm · IEEE Trans. Computers 1984
Integrated circuit design › digital circuit design › arithmetic circuit design › multiplier design
bit-sequential multiplier
0.011984
The VLSI Implementation of a Reed-Solomon Encoder Using Berlekamp's Bit-Serial Multiplier Algorithm · IEEE Trans. Computers 1984

Methods — techniques the papers use, named apart from their topics

dual basis representation · 0.0berlekamp bit-serial multiplication · 0.0
YearPublicationVenuePosition
1984 The VLSI Implementation of a Reed-Solomon Encoder Using Berlekamp's Bit-Serial Multiplier Algorithm
abstract
Berlekamp has developed for the California Institute of Technology Jet Propulsion Laboratory (JPL) a bit-serial multiplication algorithm for the encoding of Reed-Solomon (RS) codes, using a dual basis over a Galois field. The conventional RS encoder for long codes often requires lookup tables to perform multiplication of two field elements. Berlekamp's algorithm requires only shifting and EXCLUSIVE OR operations. It is shown in this paper that the new dual-basis (255,223) RS encoder can be realized readily on a single VLSI chip with NMOS technology.
In-Shek Hsu, Irving S. Reed, Trieu-Kien Truong, Chiunn-Shyong Ye, Leslie J. Deutsch
IEEE Trans. Computers5