Nowadays the integrated circuit is usually in need of various voltage supports. To efficiently manage the power demand, numbers of power modules are integrated together to form a power management unit (PMU). Since each power module has its own spec, the controller inside the power module is usually independent. The independent controller with its own signal process scheme definitely occupies certain circuit area, which is not area efficient as the number of power module increases inside the PMU. Therefore, a controller sharing concept is proposed for saving the circuit area. The controller sharing solution is stemmed from the time multiplexing concept. Based on the discrete feature of the digital control, several hardware segments of the controller can be shared for different power modules without affecting individual performance. Detail of the controller sharing model in time domain is built on MATLAB Simulink software to verify the feasibility of the controller sharing mechanism.

The development of radar technology has always been a hot issue. In recent years, due to the popularization of Advanced Driver Assistance Systems (ADAS), such as autonomous driving system and collision avoidance system, the requirements for radar technology are increasing rapidly. Through the radar system and the digital signal processing, we can get the object's information, such as range, velocity and angle. This paper will focus on the DOA (Direction of Arrival) which is called angle detection in general. The MUSIC (MUltiple SIgnal Classification) algorithm is a kind of super resolution algorithm for angle searching. In MUSIC algorithm, EVD (Eigenvalue Decomposition) has the most computation load. Therefore, we use cyclic Jacobi method to implement EVD processor, which can achieve hardware simplification. In order to reduce the latency, this paper propose using the neural network model to calculate the values of arctangent, sine and cosine function instead of using the traditional CORDIC (Coordinate Rotation Digital Computer) method. The proposed NN-based Cyclic Jacobi EVD processor was operated at 250 MHz in TSMC 90 nm CMOS technology. The total latency of the system is 1.25 us, and the total gate counts are 104.401k.

Recently, emerging mobile computing requires the high integration of hearing aids into a single system-on-chip. Modern hearing aid systems include a frequency decomposer, noise reduction, feedback cancellation, auditory compensation, and intelligent adaptation. The majority of existing works concentrated on improving the performance and efficiency on a single-signal processing block or one-sided effect. These works lacked comprehensive discussions on system-wide aspects regarding the overall impacts. To design an optimal hearing aid system, frequency decomposers, or the filter banks that dominate in hearing aid systems, are the first priority. We propose a systematic relaxation of the ANSI S1.11 specification and its design procedure for filter banks. The proposed design procedure overcomes the drawbacks of previous works and changes the five performance indices of the filter bank: delay, complexity, sub-band rate reduction, ripples of synthesized output, and prescription matching errors. These performance indices help system or algorithm designers in selecting a beneficial system-relaxed filter bank to achieve optimal hearing aids. The proposed multirate filter bank using the resampling method provides an efficient, low complexity, and delay-constrained computing architecture. Finally, seven design cases are used to demonstrate the proposed method, and comprehensive discussions of the five performance indices are presented.

Based on an error-flattened, non-uniform-region linear-approximation algorithm, this brief proposes a low-error and a cost-efficient design procedure for realizing an optimized shift-and-add Logarithmic Unit (LU), which uses minimum hardware to meet the desired error constraint for embedded graphics systems. Mathematically, this brief first derives two solutions of the error-flattened algorithm. Subsequently, for an error constraint, the minimum number of approximation regions, n, the corresponding i th interpolation coefficients (ai, bi), and the regional endpoints (xi-1, xi), 1 ≤ i ≤ n, are obtained accordingly. Using the unique properties of the logarithmic function, spacing of xi is non-uniform to make errors in each region consistent. Carefully examining the cost of the applied add/sub network, a low-cost candidate for a shift-and-add LU is determined. Next, a cost exploration process, which gradually increases n, is performed. A large number of regions results in a more accurate conversion algorithm that might tolerate more implementation errors by using simple hardware whose cost is lower than that of the inferior candidate. After exploring the cost based on error tolerance, the proposed design procedure finally generates a hardware to meet the desired error constraint. Slightly modifying the regional endpoint xi increases hardware efficiency at the cost of increased error. Proposed circuits were synthesized in UMC 65RVT CMOS technology. Compared to state-of-the-art shift-and-add logarithmic converters, simulation results reveal that the proposed design saves approximately 12.7-51.1 percent area of polynomial approximation and improves approximately 1-14-dB SNR gain while achieving a tighter error constraint.

This paper presents the multirate and re-sampling techniques to realize a low-delay, 18-band quasi-ANSI filter bank for digital hearing aids, which not only achieves a rather low computation complexity without a significant increase in the latency, but reduces greatly the total computation complexity for sub-band signal processing followed by the filter bank, such as noise reduction as well as wide dynamic range compression (WDRC). Researches done in the literature all focused on how to reduce the computation complexity of the filter bank. In particular, with the efficient multirate and interpolated FIR (IFIR) approaches for a 10-ms, 18-band quasi-ANSI filter bank, approximately 93% of the multiplications are saved, compared that with a straightforward parallel FIR filters architecture. However, they did not consider the computation complexity of the sub-band signal processing. In this paper, we first investigate realizing the FIR filter bank efficiently by using the multirate re-sampling techniques. To reduce the complexity, the optimized re-sampling factor for each filter band is explored carefully. Then, with the resampling technique, an efficient multirate quasi-ANSI FIR filter bank architecture is proposed. Compare to the state-of-the-art quasi-ANSI filter bank, approximately 17.7% of multiplicative complexity is reduced further and, up to 25% of the total computation complexity for sub-band signal processing followed by the filter bank is saved, but with only a slight increase in latency, i.e. 13.6 ms.

This paper presents a low-power hearing aid chip which operates under near-threshold voltage region to minimize energy consumption. The proposed variable-latency design technique compensates the performance degradation under ultra-low voltage, while the proposed FIR filter computing datapath improves the energy efficiency for filter bank computation in hearing aids. The hearing aid system composed of four heterogeneous processing elements to optimize the flexibility and power consumption. The overall system was fabricated in TSMC 65nm LP process. The measured results show that the power consumption achieves 500 μW at 0.5V and 6 MHz

In this paper, an autonomous tuning method is proposed to realize optimal adaptive voltage positioning (AVP) scheme for the buck converter. The optimal AVP scheme can perform linearly fast transient response with less output capacitors compared to the traditional buck converter. The conventional wisdom of realizing the optimal AVP is to make the current sensing resistor (Ri) equal to the equivalent series resistor (Rc) of the output capacitor. However, such approach usually requires on-line system-identification algorithms or sensors that are complex and costly. Alternatively, this paper proposes a novel approach to implement the optimal AVP using a linear transition approximation (LTA) algorithm. Without using any parameter identification technique, the LTA algorithm only observes the output voltage response to adaptively adjust controller for realizing optimal linear transition during transient. The result of the proposed approach is very close to the effect of approximating Rito Rcfor an optimal AVP scheme. A buck converter using a FPGA controller that embeds the proposed algorithm is implemented. Experiment results show that the linear transient response is achieved in response to a 1-5 A step load change within 20 μs. A comparative result also shows that the optimal AVP performance is superior to the case without using the proposed algorithm.

Cloud Service is a major project that CHT currently initiated to promote. It aims to provide services to users anytime and anywhere. To achieve that, we need robust cloud technology. This paper takes FMS (Fraud Management System) as an example to depict the system migration process into the cloud service. We propose solutions to problems we encountered, software licensing issues, and other related issues. With the portable ability supporting by middleware, the underlying cross-brand components can be easily to swap, such as: various brands of web servers, application servers, operating systems, and databases. Our FMS system architecture is fully met the SaaS architecture's requirement.

Auditory compensation consumes significant power due to the computation-intensive operations in the filter bank. To reduce the complexity, a controllable filter was designed to replace the filter bank. Filter order was designed to match prescriptions within a specific error constraint with minimum computational cost. An interpolation scheme according to the variation of signal intensity was implemented to reduce the overhead of coefficients calculations. The proposed auditory compensation reduces 80% of multiplications and 30% of power consumption compared to the complexity-effective multi-rate filter bank architecture [4]. Moreover, the group delay was also reduced from 10 ms to 2.4 ms.

This paper presents a power-efficient computing platform for hearing aids. The proposed platform composes four heterogeneous processing elements. Each processing element includes one tiny RISC processor and several power-efficient hardwired accelerators. The hardwired accelerators integrate static floating-point and truncated multiplier to improve signal-to-noise ratio and reduce computational complexity. Compared to the post-truncate multiplication in FIR filter, the proposed static floating-point datapath reduces 50.8% area and improves 2.2 dB SNR simultaneously.

Recently, many embedded systems adopt the heterogeneous multi-core processors, such as the TI OMAP and the IBM Cell BE, to allow offloading computation-intensive tasks from the MPU to the DSP for satisfying the increasing complexity of the emerging DSP streaming applications, such as the audio/video coding. By conventional parallel programming, task management is handled by the MPU with the OS or runtime assist. However, the thick OS stack or the laborious task management will significantly degrade the performance. This paper proposed a dedicated programmable smart stream controller, conforming to the streaming computation, to offload the task management from the MPU to greatly reduce runtime overhead. The smart stream controller provides a set of simple and high-level APIs to facilitate parallel programming on the heterogeneous multi-core processors. In our 512×512 JPEG encoding simulations, the proposed dedicated smart stream controller achieves up to 80% performance improvement compared to its software counterpart, i.e. implementing a runtime on MPU. Additionally, the performance scalability and capability of the smart stream controller to take advantage of architectural parallelism, adapting to varying number of DSP cores, are also presented.

This paper presents an event-driven adaptive voltage scaling (AVS) system, where a vanguard collaborates with a rearguard to find a minimal supply voltage. While the vanguard is responsible for the slack cycle time estimation, the rearguard allows voltage over-scaling with a variable-latency datapath. An improved vanguard is proposed based on online static timing analysis (STA), which monitors a scalable number of critical path candidates at run time. In our simulations, the delay estimation error is within 10%, which is relatively small compared to critical path variations of prevailing multi-Vt designs in deep-submicron era. A testchip with a 32-bit tiny RISC has been fabricated with the TSMC 65nm LP process technology to demonstrate the effectiveness.

Dynamic range compression (DRC) is an essential function in digital hearing aids, which have stringent power consumption constraints. This work minimized the complexity of the DRC algorithm through adopting functional approximation for those involved nonlinear operations. The tradeoff between computation reduction and approximation error was explored for reducing hardware cost without introducing audible artifact. Moreover, finite wordlength analysis is conducted for the wordlength minimization and further complexity saving. The experimental result shows that our design totally reduces 96% computing complexity of the straightforward implementation without introducing audible difference in the output signals. Compared with other approximation methods, our design also requires lower hardware complexity.

Conventional timing-optimized synchronous circuit is designed and constrained by the longest critical path delay, i.e. the worst-case design. However, the path delay of the circuit is absolutely data-dependent. In the example of an 8-bit multiplier simulation, for the 10,000 random input patterns, only about 1% of the input patterns exercise the critical path. This fact motivates us to exploit data-dependent latency of the functional unit to achieve significant energy reduction with negligible performance degradation. In this paper, we propose a design flow for the energy-efficient, variable-latency functional unit which exploits the data-dependent latency. In the 8-bit signed Booth-Wallace multiplier simulation (clock period: 1.2ns @UMC 90nm CMOS cell library), the proposed design can save energy by 21% with only 0.17% performance degradation. Besides, compared to other popular energy reduction technique, the pipelined architecture, for the classical 5-stage RISC processor, the proposed technique improves about 23-28% energy-delay metric performance efficiency.

This paper presents an ANSI S1.11-compliant filter bank for digital hearing aids, of which the power consumption is minimized through algorithmic, numerical and architectural optimizations. This filter bank has been implemented and fabricated using the TSMC 0.13 mum CMOS technology. The transistor-level simulations show that the power dissipation is only 79 mu W for 24 KHz & 18-band audio processing.

Modern architectures exploit task level parallelism to improve their performance in a cost-effective manner. However, task synchronization and management is time consuming and wastes computing resources especially on application-specific architectures, such as DSP. In this paper, we propose a smart coprocessor interface that helps to offload the task management job from MPU or DSP. In our simulations, our approach can improve the overall performance of a dual-core platform by 57%. The hardware overhead of the interface is only 1.56% of the DSP core.

This paper describes a complexity-effective design of auditory compensation, which is the most important building block in digital hearing aids. A multi-rate architecture and the filter bank design thereof are proposed to significantly reduce the data rates of the band-limited channels and thus the computational complexity. Several optimizations are discussed to further simplify the implementation of the dynamic range compressors in the multi-rate auditory compensation. In an 18-band 24-KHz digital hearing aid, 94% multiplications and additions are saved from a straightforward filter bank design. Moreover, the computation and memory requirements of the dynamic range compressor of each band are reduced to only 16% and 1% respectively.

A scalar (single-issue) processor executes one instruction at a time and its functional units (ALU, multiplier, and shifter, etc) are never concurrently exercised. Modern processors issue multiple instructions simultaneously (i.e. superscalar or VLIW) to improve their functional unit utilization but the cost is considerably high. In this paper, an alternative is described to activate multiple functional units concurrently by issuing a composite instruction on cascaded functional units. Besides, an automatic generator for application-specific composite functional units is presented. In our simulation with popular DSP applications, 35% increase on the operations per cycle can be simply obtained with identical functional units. Moreover, our proposed approach saves up to 16.5% and 31.6% power on scalar and VLIW respectively for comparable performance.

The performance of single-issue RISC cores can be improved significantly with multi-issue architectures (i.e. superscalar or VLIW) by activating the parallel functional units concurrently. However, they suffer high complexity or huge code sizes. In this paper, we borrow some ideas from old vector machines and propose a novel DSP architecture with very compact codes. In our simulations, the DSP has comparable performance to a 5-issue VLIW core with identical computing resources. However, its code sizes are greatly reduced. The DSP core has been implemented in the TSMC 0.13 mum CMOS technology, where the operating frequency is 305MHz and the core size is 1.45 times 1.4 mm2including 12KB on-chip memory.

FPGA prototyping is preferred over software simulations for its more convincing & realistic behaviours and fast simulation time. However, it is usually possible after the RTL design is done, which prevents extensive design space exploration. This paper describes an early-stage FPGA prototyping flow, which starts from C sources, through hardware/software partitioning with transaction-level modelling (TLM), to the RTL design. The paper also proposed a FPGA-customized multithreaded emulation engine for TLM prototyping. Compared with the OpenRISC core, the proposed engine saves 43.08% datapath complexity while improving the operating frequency by 60.67%. Moreover, our FPGA prototype for JPEG at TLM can compress 37.16 color QCIF frames per second, which is 4.5times faster than SystemC simulation on a 3GHz PentiumD PC

This paper proposes a virtual cluster architecture, which executes multi-cluster VLIW programs with a reduced number of clusters in a time-sharing fashion. The interleaved sub-VLIWs help to hide instruction latencies significantly, and thus the proposed virtual cluster will have advantages of (1) reduced forwarding complexity in the processor datapath, (2) improved programming model for further code optimizations, and (3) supporting composite instructions without any extra functional unit. In our experiments with a 4-cluster VLIW DSP, the 28 forwarding paths inside a cluster are completely eliminated, which contributes to savings of 21.71% delay and 17.56% silicon area. Moreover, the virtual cluster has been verified to have better efficiency on its code sizes and execution times for its improved programming model for various DSP kernels.

In this paper, we adopt a restricted Gaussian elimination on the Hankel structured augmented syndrome matrix to reinterpret an early stopped version of the Berlekamp–Massey algorithm in which only$(t + e)$iterations need to be performed for the decoding of BCH codes up to$t$errors, where$e$is the number of errors actually occurring with$e \leq t$, instead of the$2t$iterations required in the conventional Berklekamp–Massey algorithm. The minimality of$(t + e)$iterations in this early stopped Berklekamp–Massey (ESBM) algorithm is justified and related to the subject of simultaneous error correction and detection in this paper. We show that the multiplicative complexity of the ESBM algorithm is upper bounded by$(te+ e^{2} - 1) \forall e \leq t$and except for a trivial case, the ESBM algorithm is the most efficient algorithm for finding the error-locator polynomial.

In this paper, we adopt a restricted Gaussian elimination on the Hankel structured augmented syndrome matrix to reinterpret an early-stopped version of the Berlekamp-Massey algorithm in which only (t + e) iterations are needed to be performed for the decoding of BCH codes up to t errors, where e is the number of errors actually occurred with e les t, instead of the It iterations required in the conventional Berlekamp-Massey algorithm. The minimality of (t + e) iterations in this early-stopped Berlekamp-Massey (ESBM) algorithm is justified and related to the subject of simultaneous error correction and detection in this paper. We show that the multiplicative complexity of the ESBM algorithm is upper bounded by (te + e2- 1)foralle les t and except for a trivial case, the ESBM algorithm is the most efficient algorithm for finding the error-locator polynomial.

This paper presents a DSP core for multi-core media SoC, which is optimized to execute a set of signal processing tasks very efficiently. The fully-programmable core has a data-centric instruction set and a corresponding latency-insensitive micro-architecture, where the hardware design is optimized concurrently with its automatic software generator. The proposed DSP core has 3/spl times/ performance (in cycles) of those found in commercial dual-core application processors with similar computing resources. The silicon implementation in UMC 0.18/spl mu/m 1P6M CMOS technology operates at 314MHz and consumes only 52mW average power.

This paper presents a programmable FIR core with a compact adder-based computing engine and an automatic code generator. The FIR core saves 50% area of conventional MAC-based cores in the 0.13/spl mu/m implementation. Besides, the complexity-aware code generator synthesizes optimized FIR programs for a user-defined sampling period. It explores an optimal scaling factor with common subexpression elimination automatically. In our simulations, the proposed approach reduces about 10% /spl sim/ 18% computing time of MAC-based FIR cores with comparable filtering performance.

This paper presents a unified processor core with two operation modes. The processor core works as a compiler-friendly MIPS-like core in the RISC mode, and it is a 4-way VLIW in its DSP mode, which has distributed and ping-pong register organization optimized for stream processing. To minimize hardware, the DSP mode has no control construct for program flow, while the data manipulation RISC instructions are executed in the DSP datapath. Moreover, the two operation modes can be changed instruction by instruction within a single program stream via the hierarchical instruction encoding, which also helps to reduce the VLIW code sizes significantly. The processor has been implemented in the UMC 0.18um CMOS technology, and its core size is 3.23mmx3.23mm including the 32KB on-chip memory. It can operate at 208MHz while consuming 380.6mW average power.

As the VLSI technology advances continuously, ASIC can easily achieve the required performance and most of them are actually over-designed. Thus, architecture shrinking is inevitable in optimal designs especially when supply voltages are getting lower. However, conventional designs starting from minimization of algorithmic operations (e.g. multiply) may not always lead to optimal architectures, for the wires and the interconnection complexity significantly grow and have become predominant. This paper explores algorithms and architectures for the 2-D transform in H.264/AVC, of which the operations are very simple (i.e. only shift and add). We have shown that fewer operations do not always result in more compact designs. In our experiments with the UMC 0.18 /spl mu/m CMOS technology, the most straightforward matrix multiplication without separable 2-D operation or any fast algorithm has the best area efficiency for DI-size (720/spl times/480) video at 30 fps. It saves 48%, 34%, and 16% silicon area of the previous works respectively.

The multimedia SoC usually integrates programmable digital signal processors (DSP) to accelerate data-intensive computations. But the DSP and the host processor (e.g. ARM) are both designed for standalone uses, and they must have overlapped functionalities and thus some redundant components. In this paper, we propose a compact DSP core for dual-core multimedia SoC and its complete software development tools. The DSP core contains a dataflow engine that is composed of off-the-shelf memory modules with limited ports, and we have investigated software techniques extensively to reduce the hardware complexity as the principles of VLIW processors. Moreover, the DSP is equipped with novel static floating-point units to emulate expensive floating-point DSP operations at low cost. In our experiments, this core has about thrice the performance (estimated in execution cycles) of Analog Devices ADSP-218x with similar computing resources. Our first prototype in the 0.35um CMOS technology operates at 100MHz and consumes 122mW power. The core size is 2.8mm2 including an embedded DMA controller and the AMBA AHB interface.

An efficient implementation of a parallel version of the Feng-Rao algorithm on a one-dimensional systolic array is presented in this paper by adopting an extended syndrome matrix. Syndromes of the same order, lying on a slant diagonal in the extended syndrome matrix, are scheduled to be examined by a series of cells simultaneously and, therefore, a high degree of concurrency of the Feng-Rao algorithm can be achieved. The time complexity of the proposed architecture is m+g+1 by using a series of t+[g-1/2]+1, nonhomogeneous but regular, effective processors, called PE cells, and g trivial processors, called D cells, where t is designed as the half of the Feng-Rao bound. Each D cell contains only delay units, while each PE cell contains one finite-field inverter and, except the first one, one or more finite-field multipliers. Cell functions of each PE cell are basically the same and the overall control circuit of the proposed array is quite simple. The proposed architecture requires, in total, t+[g-1]+1 finite-field inverters and (t+[(g'1)/2])(t+[(g-1)/2]+1)/2 finite-field multipliers. For a practical design, this hardware complexity is acceptable.