This work proposes an encrypted controller framework for closed-loop control systems with nonlinear dynamics over fully homomorphic encryption (FHE). Unlike differential privacy and output masking, FHE is a cryptographic primitive that provides assumption-based confidentiality guarantees under standard hardness assumptions. We observe that existing encrypted control frameworks remain largely limited to linear open-loop systems, primarily due to two key challenges: rapid ciphertext noise accumulation in feedback loops and the substantial computational overhead of nonlinear operations. In control systems, feedback is essential for real-time error correction, while nonlinear characteristics are critical for accurately modelling complex system behaviours. To address these challenges, we propose ENClose, a novel encrypted control framework that enables low-latency execution of both feedback control and nonlinear function evaluation. Specifically, ENClose introduces a low-latency homomorphic nonlinear computation framework that accelerates functional bootstrapping (FBS) by combining function segmentation with tree-based encrypted selection. This framework not only mitigates noise accumulation in encrypted feedback loops but also significantly improves the efficiency of FBS under high-precision settings, meeting the computational demands of dynamic control systems. Experimental results show that ENClose achieves a 3× to 20× speedup over state-of-the-art encrypted controllers. We validate ENClose through realworld applications, including multi-vehicle formation, spring–mass–damper control, and anomaly recovery, where the results demonstrate high-precision tracking and successful reconvergence after anomalies.

Fully Homomorphic encryption (FHE) enables high-level security but with a heavy computation workload, necessitating software-hardware co-design for aggressive acceleration. Recent works on specialized accelerators for HE evaluation have made significant progress in supporting lightweight RNS-CKKS applications, especially those with high-density in-memory computing techniques. To fulfill higher computational demands for more general applications, this article proposes multicluster HE accelerating system (MCHEAS), an accelerating system comprising multiple in-situ HE processing accelerators, each functioning as a cluster to perform large-parameter RNS-CKKS evaluation collaboratively. MCHEAS features optimization strategies including the synchronous, preemptive swap, square-diagonal, and odd-even index separation. Using these strategies to compile the computation and transmission of number theoretic transform (NTT) coefficients, the method optimizes the intercluster data swaps, a major bottleneck in NTT computations. Evaluations show that under 1 GHz, with different intercluster data transfer bandwidths, our approach accelerates NTT computations by 26.40% to 51.75%. MCHEAS also improves computing unit utilization by 10.30% to 33.97%, with a maximum peak utilization rate of up to 99.62%. MCHEAS achieves 17.63% to 34.67% speedups for HE operations involving NTT, and 15.12% to 30.62% speedups for demonstrated applications, while enhancing the computing units’ utilization by 5.18% to 21.87% during application execution. Furthermore, we compare MCHEAS with SOTA designs under a specific intercluster data transfer bandwidth, achieving up to$81.45\times $their area efficiencies in applications.

Fully homomorphic encryption (FHE) and post-quantum cryptography (PQC) heavily rely on number theoretic transform (NTT) to accelerate polynomial multiplication, However, most existing NTT accelerators lack flexibility when the underlying modulus and polynomial lengths change. Current designs often store twiddle factors in on-chip storage, facing a noticeable drawback when frequent parameter changes occur, leading to a potential 50% decrease in computation speed due to the input bandwidth limitations. To address this challenge, we propose ESC-NTT, a fully-pipelined and flexible architecture for handling NTTs with varying parameters. ESC-NTT, a complete custom architecture, continuously performs$N$-point (inverse) NTT, negacyclic NTT (NCN), and inverse NCN (INCN) without introducing bubbles during modulus and NTT length switches. Additionally, we introduce a twiddle factor generator (TFG) module to replace on-chip factor storage and save 68.7% twiddle factors' bandwidth compared to inputting every factor. In the experiment, ESC-NTT is implemented on a Xilinx Alveo U280 FPGA and synthesized in a 28 nm CMOS technology. In the case of frequent modulus switching and same on-chip storage, the calculation speed of ESC-NTT is 1.05× to 241.39× that of existing FHE accelerators when performing 4096-point NTT.

Energy-efficient machine-learning and physical unclonable function (PUF) becomes popular in Internet-of-Things (IoT) applications for saliency detection and privacy protection at sensor node. A machine-learning and PUF engine for IoT applications is presented in this work with a current mirror cross-bar (CMCB) array being a shared core, reducing silicon area. A novel dimension expansion technique is proposed to increase weight matrix dimension beyond the physically implemented array with small hardware and energy overhead. A signed multiply-and-accumulation is realized in CMCB with differential current path and 2-phase conversion. The proposed engine achieves an error rate of 6.34% on MNIST digit recognition task with an energy efficiency of 2.86 TOPS/W. The PUF achieves a native BER of 2.3% across corners and extremely low area/CRP of 4.17×10-59μm2/CRP.

In this work, we present a novel design of physical unclonable function (PUF) based on the topology of current mirror array (CMA). The proposed strong PUF exploits the randomness in the current mirror transistors and generates the response bit by comparing the accumulated current values. Thresholding and reference current are used to increase the reliability of the proposed PUF without requiring additional hardware resources. The proposed PUF structure is also analysed in terms of its difficulty of model building for measurement-prediction attack. Measurement results on 0.35μm test chips demonstrate that the proposed PUF outperforms other state-of-the-art designs with smaller area/bit of 9 × 10−36μm2 and lower native bit error rate (BER) of 0.16%.

A machine learning co-processor in 0.35μm CMOS for motor intention decoding in the brain-machine interfaces is presented in this paper. Using Extreme Learning Machine algorithm, time delayed sample based feature dimension enhancement, low-power analog processing and massive parallelism, it achieves an energy efficiency of 290 GMACs/W at a classification rate of 50 Hz. A portable external unit based on the proposed co-processor is verified with neural data recorded in monkey finger movements experiment, achieving a decoding accuracy of 99.3%. With time-delayed feature dimension enhancement, the classification accuracy can be increased by 5% with limited number of input channels.