Demo Data from EDBT 2026 / reviewers in the wild / expert
Polen Kission
dblp:49/6864
· DBLP profile ↗
5ranked-venue papers
2as first author
0since 2021 · last 1998
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 1 first-authorSoftware engineering, systems software and programming languages · 2 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 89% Integrated circuit design · 11% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
high-level synthesis |
0.0 | 2 | 1996 | Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis · DAC 1996 Structured Design Methodology for High-Level Design · DAC 1994 |
Electronic design automation › design methodology
structured design methodologies |
0.0 | 1 | 1994 | Structured Design Methodology for High-Level Design · DAC 1994 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 1996 | Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis · DAC 1996 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1998 | Architectural Simulation in the Context of Behavioral SynthesisabstractThis paper deals with integrating an interactive simulator within a behavioral synthesis tool, thereby allowing concurrent synthesis and simulation. The resulting environment provides a cycle based simulation of a behavioral module under synthesis. The simulator and the behavioral synthesis are based on a single model that allows one to link the behavioral description and the architecture produced by synthesis. The basic simulation-synthesis model is extended in order to allow for concurrent architectural simulation of several modules under synthesis. This paper also discusses an implementation of this concept resulting in a simulator, called AMIS. This tool assists the designer for understanding the results of behavioral synthesis and for architecture exploration. It may also be used to debug the behavioral specification. Abderrazak Jemai, Polen Kission, Ahmed Amine Jerraya |
DATE | 2 |
| 1997 | Embedded architectural simulation within behavioral synthesis environmentabstractThis paper introduces one way to integrate an interactive simulator within a behavioral synthesis tool, thereby allowing concurrent synthesis and simulation. Such a simulator performs dynamic analysis and time evaluation. This paper also discusses an implementation of this concept resulting in a simulator, called AMIS. This tool assists the designer for understanding the results of behavioral synthesis and for architecture exploration. Abderrazak Jemai, Polen Kission, Ahmed Amine Jerraya |
ASP-DAC | 2 |
| 1996 | Combined Control Flow Dominated and Data Flow Dominated High-Level SynthesisabstractThis paper presents the design of a Videophone Coder-Decoder Motion Estimator using two High-Level Synthesis tools. Indeed, the combination of a Control Flow Dominated part (complex communication protocol) with a Data Flow Dominated part (high throughput computations) makes this circuit difficult to be synthesized by a single HLS tool. The combination of two HLS tools for the high-level design of this operator required the definition of a sophisticated design flow allowing mixed-level and multi-language simulations. When compared to design starting from RTL specifications, HLS induces only a negligible area overhead of 5%, and provides gain in description length (divided by 5), design time and flexibility. Elisabeth Berrebi, Polen Kission, Serge Vernalde, S. De Troch, Jean-Claude Herluison, Jean Fréhel, Ahmed Amine Jerraya, Ivo Bolsens |
DAC | 2 |
| 1994 | Structured Design Methodology for High-Level DesignabstractInternational audience Polen Kission, Ahmed Amine Jerraya |
DAC | 1 |
| 1994 | Accelerating the design process by using architectural synthesisabstractThis paper deals with using architectural synthesis and structured design methodology in order to accelerate the design process. Such task will be achieved using AMICAL, an architectural synthesis tool allowing the design of complex systems. The design starts with a behavioral description and a library of functional units. The library may include standard components and/or complex sub-systems that may be designed using other design tools and methodologies or using AMICAL itself. A design example, namely a PID (Proportional Integral Derivative) is used to illustrate the methodology. The synthesis of the PID is done using several functional unit libraries. The most interesting synthesis results are those obtained on having a sub-system (fixed-point unit) designed using AMICAL, and re-used as a functional unit for the synthesis of the full design.> Polen Kission, Ahmed Amine Jerraya |
RSP | 1 |