Clock meshes possess inherent low clock skews and excellent immunity to process-voltage-temperature variations, and have increasingly found their way to high-performance integrated circuit designs. However, analysis of such massively coupled networks is significantly hindered by the sheer size of the network and tight coupling between non-tree interconnects and large numbers of clock drivers. While the SPICE simulation of large clock meshes is often intractable, standard interconnect model order reduction algorithms also fail due to the large number of input/output ports introduced by clock drivers. The presented approach is motivated by the key observation of the steady-state operation of the clock networks while its efficiency is facilitated by exploringnewclock-mesh specific harmonic-weighted model order reduction algorithm and locality analysis via port sliding. The scalability of the analysis is significantly improved by eliminating the need for computing infeasible multi-port passive reduced order interconnect models with large port count and decomposing the overall task into very tractable and naturally parallelizable model generation and fast Fourier transform/inverse-fast Fourier transform operations, all on a per driver or per sink basis. We demonstrate the application of our approach by feasibly analyzing large clock meshes with excellent accuracy.

Decap allocation are the primary methods for addressing the dynamic voltage noise problem of on-chip power networks. When space in the immediate proximity of a hot spot is constrained, simply adding decoupling capacitance without improving the local wiring is ineffective. Based on this key observation we proposed an effecient co-optimization of decap allocation and local wiring enhancement. The method solves a linear program (LP) iteratively and is based on the decap budgeting algorithm [10]. Experimental results on two actual chip designs demonstrate the area and run-time efficiency of the co-optimization algorithm. Moreover, it provides excellent solutions even in cases where decap allocation alone fails to provide a feasible solution.

We propose a novel and efficient incremental analysis technique for 'what-if analysis of on-chip power distribution networks (PDN). Effect of local modifications to a PDN, including local topology changes, can be quickly analyzed without need for very expensive re-analysis of the entire modified network. We borrow ideas from a fictitious domain method that has been successfully used in solving partial differential equations arising from inhomogeneous problems in mechanics. The effect of local wiring modifications in several PDN regions is mimicked by applying fictitious currents at the boundaries of these regions in the original unmodified network. The fictitious currents are calculated from component sub-problems in a low-computation iterative procedure. The practicality of this method for use in what-if analysis is demonstrated with several large power networks from actual industrial designs. It analyzes a modified network with few million changes in a fraction of time it would take for a complete re-analysis.

Clock meshes posses inherent low clock skews and excellent immunity to PVT variations, and have increasingly found their way to high-performance IC designs. However, analysis of such massively coupled networks is significantly hindered by the sheer size of the network and tight coupling between non-tree interconnects and large numbers of clock drivers. The presented Harmonic-weighted model order reduction algorithm is motivated by the key observation of the steady-state operation of the clock networks, and its efficiency is facilitated by the locality analysis via port sliding. The scalability of the analysis is significantly improved by eliminating the need of computing infeasible multi-port passive reduced order interconnect models with large port count. And the overall task is decomposed into tractable and naturally parallelizable model generation and FFT/Inverse-FFT operations, all on a per driver or per sink basis.

For statistical timing and power analysis that are very importantproblems in the sub-100nm technologies, stochastic analysis of power grids that characterizes the voltage fluctuations due to process variations is inevitable. In this paper, we propose an efficient algorithm for the variational analysis of large power grids in the presence of a significant number of Gaussian intra-die process variables that are correlated. We consider variations in the power grid's electrical parameters as spatial stochastic processes and express them as linear expansions in an orthonormal series of random variables using the Karhunen-Loéve(KLE) method. The voltage response is then represented as an orthonormal polynomial series and the coefficients are obtained optimally using the Galerkin method. We propose a novel method to separate the stochastic analysis for the random variables that effect only the inputs (e.g, drain currents) and for those that effect the system parameters as well (e.g., conductance, capacitance). We show that this parallelism can result in significant speed-ups in addition to the speed-ups inherent to Galerkin-based methods. Our analysis has been applied to several industrial power grids and the results show speed-ups of up to two orders of magnitude over Monte Carlo simulations for comparable accuracy.

We propose a novel and efficient charge-based decoupling capacitance budgeting algorithm. Our method uses the macromodeling technique and effective radius of decoupling capacitance to reduce the size of the problem. We formulate the nonlinear optimization into a linear program (LP) by integrating the nodal equations across a time period of interest and through certain approximations. To reduce the error caused by linearization, we do multiple iterations of the linear program. Experimental results demonstrate that, with the proposed algorithm, even very large power networks (eg. 5 million nodes) can be optimized in a couple of hours with 1-2 transient analyses. Comparison of our algorithm with another heuristic method shows area efficiency and run time advantage of our method.

This paper presents a linear system formulation for evaluating full-chip electromigration (EM) risk in general (straight line, tree, and mesh) wiring topologies, considering stress-induced backflow of metal ions. The system of equations is based on stress gradients and mass displacements in wire segments as variables, and is formulated for efficient implementation in computer-aided design (CAD) tools for designing high-performance microprocessor chips involving large databases. Derived from a well-known hydrostatic stress model in tree interconnects (J. Appl. Phys., vol. 47, no. 4, p. 1203, 1976; IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 18, no. 5, p. 576, 1999; Microelectron. Reliab., vol. 39, no. 11, p. 1667, 1999), the system is readily modified for evaluating EM risk in mesh topologies. The authors demonstrated a significant increase in the predicted lifetime of a high-performance microprocessor with the application of the proposed method to filter out risk-free structures from subsequent statistical EM risk calculations.

Power-distribution networks of very large-scale integrated (VLSI) chips should be designed carefully to ensure reliable performance. A sound power network requires an adequate number of power-supply input connections (pads and pins). Placing them at the best vantage locations helps to reduce the number of supply connections necessary for obtaining quality power distribution. This paper addresses the problem of finding an optimum set of pads, pins, and on-chip voltage regulators, and their placement in a given power-supply network, subject to constraints on the voltage drops in the network and maximum currents through the pads, pins, and regulators. The problem is modeled as a mixed-integer linear program (MILP) with the help of macromodeling techniques. Two new heuristics, in addition to the commonly used branch-and-bound technique, are proposed to make the problem tractable. The effectiveness of the proposed technique is demonstrated on several real chips and memories used in low-power and high-performance applications.

In this paper, we investigate the impact of interconnect and device process variations on voltage fluctuations in power grids. We consider random variations in the power grid's electrical parameters as spatial stochastic processes and propose a new and efficient method to compute the stochastic voltage response of the power grid. Our approach provides an explicit analytical representation of the stochastic voltage response using orthogonal polynomials in a Hilbert space. The approach has been implemented in a prototype software called OPERA (Orthogonal Polynomial Expansions for Response Analysis). Use of OPERA on industrial power grids demonstrated speed-ups of up to two orders of magnitude. The results also show a significant variation of about /spl plusmn/35% in the nominal voltage drops at various nodes of the power grids and demonstrate the need for variation-aware power grid analysis.

High performance circuits are facing increasingly severe signal integrity problems due to crosstalk noise and crosstalk noise awareness has become an integral part of static timing analysis (STA). Existing crosstalk noise aware STA methods compute noise induced delay uncertainty on a net by net basis and in a pessimistic way, without considering the overlap bounds of the victim and aggressor timing windows and realistic delay impact on early and late signal arrival times. Since crosstalk induced delay on individual nets contribute cumulatively on data and clock paths, even small amounts of pessimism in computation can add up to produce several unrealistic timing violations. Unlike glitch noise analysis where noise often attenuates during propagation, quality of delay noise analysis is severely affected by any pessimism in noise estimation and can unnecessarily cost valuable silicon and design resources for fixing unreal violations. In this paper, we propose two temporal techniques to reduce pessimism in crosstalk noise aware STA. The first method, "effective delay noise", is a net based method where the exact overlap points of victim and aggressor timing windows are considered to obtain the part of delay noise that actually impacts early and late signal arrival times. The second method, "path based delay noise", is a path based method where the reduced arrival uncertainty of the nets of a given path are utilized for pessimism reduction. We also propose a novel "uncertainty propagation" technique as part of the second method, which results in an iteration free crosstalk noise aware STA of the path with significantly reduced pessimism. The two techniques are combined in a proposed methodology that is compatible with existing industrial static timing analyzers with very little computational overhead compared to the traditional noise aware STA and a significant improvement in eliminating unreal violations. The proposed techniques resulted in 77% reduction of worst case negative slack and 57% reduction in the number of failing paths in the setup analysis of a 90nm industrial design.

Power supply integrity analysis is critical in modern high perfor-mance designs. In this paper, we propose a stochastic approach to obtain statistical information about the collective IR and LdI/dt drop in a power supply network. The currents drawn from the power grid by the blocks in a design are modelled as stochastic processes and their statistical information is extracted, including correlation infor-mation between blocks in both space and time. We then propose a method to propagate the statistical parameters of the block currents through the linear model of the power grid to obtain the mean and standard deviation of the voltage drops at any node in the grid. We show that the run time is linear with the length of the current wave-forms allowing for extensive vectors, up to millions of cycles, to be analyzed. We implemented the approach on a number of grids, including a grid from an industrial microprocessor and demonstrate its accuracy and efficiency. The proposed statistical analysis can be use to determine which portions of the grid are most likely to fail as well as to provide information for other analyses, such as statistical timing analysis.

Power delivery networks of VLSI chips require adequate input supply connections to ensure reliable performance. This paper addresses the problem of finding an optimum set of pads, pins, and on-chip voltage regulators, and their placement in a given power supply network, subject to constraints on the voltage drops in the network and maximum currents through the pads, pins and regulators. The problem is modeled as a mixed integer linear program using macromodeling techniques and several heuristic techniques are proposed to make the problem tractable. The effectiveness of the proposed techniques is demonstrated on several real chips and memories used in low-power and high-performance applications.

High-performance digital circuits are facing increasingly severe noise problems due to cross-coupled noise injection. Traditionally, noise analysis tools use the conservative assumption that all neighbors of a net can switch simultaneously, producing the worst-case noise. However, due to logic correlations in the circuit, this worst-case noise may not be realizable, resulting in a so-called false noise failure. Some techniques for computing logic correlations have been designed targeting static CMOS circuits. However high performance microprocessors commonly use domino logic for their ALU. The domino circuits have lower noise margins than static CMOS circuits and are more sensitive to coupled noise. Any unnecessary pessimism of the noise analysis tool results in large number of false noise violations and either requires additional extensive SPICE simulations or circuit over-design. Unfortunately false noise analysis developed for static CMOS circuits fails to compute many logic correlations in domino circuits. In this paper we propose a novel technique of computing logic correlations in domino circuits. It takes into account the fact that both pull up and pull down networks of a domino gate can be in non conducting state. The proposed technique generates additional logic correlations for such states of domino gates. In order to improve the capability of logic correlation derivation technique we combine the resolution method with recursive learning algorithm. The proposed technique is implemented in an industrial noise analysis tool and tested on high performance ALU blocks.

High-performance digital circuits are facing increasingly severe signal integrity problems due to crosstalk noise and therefore the state-of-the-art static timing analysis (STA) methods consider crosstalk-induced delay variation. Current noise-aware STA methods compute noise-induced delay uncertainty for each net independently and annotate appropriate delay changes of nets onto data paths and associated clock paths to determine timing violations. Since delay changes in individual nets contribute cumulatively to delay changes of paths, even small amounts of pessimism in noise computation of nets can add up to produce large timing violations for paths, which may be unrealistic. Unlike glitch noise analysis where noise often attenuates during propagation, quality of delay noise analysis is severely affected by any pessimism in noise estimation and can unnecessarily cost valuable silicon and design resources for fixing unreal violations. In this paper, we propose a method to reduce pessimism in noise-aware STA by considering signal correlations of all nets associated with an entire timing path simultaneously, in a path-based approach. We first present an exact algorithm based on the branch-and-bound technique and then extend it with several heuristic techniques so that very large industrial designs can be analyzed efficiently. These techniques, which are implemented in an industrial crosstalk noise analysis tool, show as much as 75% reduction in the computed path delay variations.

Gate sizing is a practical and a feasible crosstalk noise correction technique in the post route design stage, especially for block level sea-of-gates designs. The difficulty in gate sizing for noise reduction is that, by increasing a driver size, noise at the driver output is reduced, but noise injected by that driver on other nets is increased. This can create cyclical dependencies between nets in the circuit with noise violations. In this paper, we propose a fast and effective heuristic postroute gate-sizing algorithm that uses a graph representation of the noise dependencies between nodes. Our method utilizes gate sizing in both directions and works in linear time as a function of the number of gates. The effectiveness of the algorithm is shown on several industrial high-performance designs.

Signal integrity closure is one of the key challenges in deep submicron physical design. In this paper, we propose a physical design methodology which includes signal integrity management through crosstalk noise analysis and repair at multiple phases of the design so that a quick noise convergence can be achieved. The methodology addresses both functional and delay noise problems in the design and is targeted for block-, platform-, and chip-level physical design of system-on-chip designs. A number of case studies are presented to illustrate the effectiveness of the proposed methodology and to provide valuable insights useful for successful signal integrity management.

Process variation has become a significant concern for static timing analysis. In this paper, we present a new method for path-based statistical timing analysis. We first propose a method for modeling inter- and intra-die device length variations. Based on this model, we then present an efficient method for computing the total path delay probability distribution using a combination of device length enumeration for inter-die variation and an analytical approach for intra-die variation. We also propose a simple and effective model of spatial correlation of intra-die device length variation. The analysis is then extended to include spatial correlation. We test the proposed methods on paths from an industrial high-performance microprocessor and present comparisons with traditional path analysis which does not distinguish between inter- and intra-die variations. The characteristics of the device length distributions were obtained from measured data of 8 test chips with a total of 17688 device length measurements. Spatial correlation data was also obtained from these measurements. We demonstrate the accuracy of the proposed approach by comparing our results with Monte-Carlo simulation.

Gate sizing is a practical and a feasible crosstalk noise repair technique in the post route design stage, especially for block level sea-of-gates designs. The difficulty in gate sizing for noise reduction is that by increasing a driver size, noise at the driver output is reduced, but noise injected by that driver on other nets is increased. This can create cyclical dependencies between nets in the circuit with noise violations. In this paper, we propose a fast and effective heuristic post-route gate sizing algorithm that uses a graph representation of the noise dependencies between nodes. Our method utilizes gate sizing in both directions and works in linear time as a function of the number of gates. The effectiveness of the algorithm is shown on several industrial high performance designs.

Signal integrity closure is one of the key challenges in DSM (Deep- SubMicron) physical design. In this paper, we propose a physical design methodology which includes signal integrity management through noise analysis and repair at multiple phases of the design so that a quick noise convergence can be achieved. The methodology addresses both functional and delay noise problems in the design and is targeted for block, platform, and chip level physical design of SoC (System-On-Chip) designs. A number of case studies are presented to illustrate the effectiveness of the proposed methodology and to provide valuable insights useful for successful signal integrity management.

One of the critical challenges in today's high-performance IC design is to take noise into account as early as possible in the design cycle. Current noise analysis tools are effective at analyzing and identifying noise in the postroute design stage when detailed parasitic information is available. However, noise problems identified at this stage of the design cycle are very difficult to correct due to the limited flexibility in design and may cause additional iterations of routing and placement which adds costly delays in its time to market. In this paper, we introduce a probabilistic preroute noise analysis approach to identify postroute noise failures before the actual detailed route is completed. We introduce new methods to estimate the RC characteristics of victim and aggressor lines, their coupling capacitances, and the aggressor transition times before routing is performed. The approach is based on congestion information obtained from a global router. Since the exact location and relative position of wires in the design are not yet available, we propose a novel probabilistic method for capacitance extraction. We present results on two high-performance microprocessors in 0.18 /spl mu/m technology that demonstrate the effectiveness of the proposed approach.

In this paper, a precorrected-fast-Fourier-transform (FFT) approach for fast and highly accurate simulation of circuits with on-chip inductance is proposed. This work is motivated by the fact that circuit analysis and optimization methods based on the partial element equivalent circuit model require the solution of a subproblem in which a dense inductance matrix must be multiplied by a given vector, an operation with a high computational cost. The grid representation enables the use of the discrete FFT for fast magnetic vector potential calculation. The precorrected-FFT method has been applied to accurately simulate large industrial circuits with up to 121 000 inductors and over 7 billion mutual inductive couplings in about 20 min. Techniques for trading off CPU time with accuracy using different approximation orders and grid constructions are also illustrated. Comparisons with a block-diagonal sparsification method are used to illustrate the accuracy and effectiveness of this method. In terms of accuracy, memory, and speed, it is shown that the precorrected-FFT method is an excellent approach for simulating on-chip inductance in a large circuit.

Noise estimation and avoidance are becoming critical, 'must have' capabilities in today's high performance IC design. An accurate yet efficient crosstalk noise model which contains as many driver/interconnect parameters as possible, is necessary for any sensitivity based noise avoidance approach. In this paper, we present a complete analytical crosstalk noise model which incorporates all physical properties including victim and aggressor drivers, distributed RC characteristics of interconnects and coupling locations in both victim and aggressor lines. We present closed-form analytical expressions for peak noise and noise width as well as sensitivities to all model parameters. We then use them model parameter sensitivities to analyze and evaluate various noise avoidance techniques such as driver sizing, wire sizing, wire spacing and layer assignment. Both our model and noise avoidance evaluations are verified using realistic circuits in 0.13/spl mu/ technology. We also present effectiveness of discussed noise avoidance techniques on a high performance microprocessor core.

The simulation of on-chip inductance using PEEC-based circuit analysis methods often requires the solution of a subproblem where an extracted inductance matrix must be multiplied by a current vector, an operation with a high computational cost. This paper presents a highly accurate technique, based on a precorrected-FFT approach, that speeds up this calculation. Instead of computing the inductance matrix explicitly, the method exploits the properties of the inductance calculation procedure while implicitly considering the effects of all of the inductors in the layout. An optimized implementation of the method has been applied to accurately simulate large industrial circuits with up to 121,000 inductors and nearly 7 billion mutual inductive couplings in about 20 minutes. Techniques for trading off the CPU time with the accuracy using different approximation orders and grid constructions are also illustrated. Comparisons with a block diagonal sparsification method in terms of accuracy, memory and speed demonstrate that our method is an excellent approach for simulating on-chip inductance in a large circuit.

Noise analysis has become a critical concern in advanced chip designs. Traditional methods suffer from two common issues. First, noise that is propagated through the driver of a net is combined with noise injected by capacitively coupled aggressor nets using linear summation. Since this ignores the non-linear behavior of the driver gate the noise that develops on a net can be significantly underestimated. We therefore propose a new linear model that accurately combines propagated and injected noise on a net and which maintains the efficiency of linear simulation. After the propagated and injected noise are correctly combined on a victim net, it is necessary to determine if the noise can result in a functional failure. This is the second issue that we discuss in this paper. Traditionally, noise failure criteria have been based on unity gain points of the DC or AC transfer curves. However, we will show that for digital designs, these approaches can result in a pessimistic analysis in some cases, while in other cases, they allow circuit operation that is extremely close to regions that are unstable and do not allow sufficient margin for error in the analysis. In this paper, we compare the effectiveness of the discussed noise failure criteria and also present a propagation based method, which is intended to overcome these drawbacks. The proposed methods were implemented in a noise analysis tool and we demonstrate results on industrial circuits.

Careful design and verification of the power distribution network of a chip are of critical importance to ensure its reliable performance. With the increasing number of transistors on a chip, the size of the power network has grown so large as to make the verification task very challenging. The available computational power and memory resources impose limitations on the size of networks that can be analyzed using currently known techniques. Many of today's designs have power networks that are too large to be analyzed in the traditional way as flat networks. In this paper, we propose a hierarchical analysis technique to overcome the aforesaid capacity limitation. We present a new technique for analyzing a power grid using macromodels that are created for a set of partitions of the grid. Efficient numerical techniques for the computation and sparsification of the port admittance matrices of the macromodels are presented. A novel sparsification technique using a 0-1 integer linear programming formulation is proposed to achieve superior sparsification for a specified error. The run-time and memory efficiency of the proposed method are illustrated on industrial designs. It is shown that even for a 60 million-node power grid, our approach allows for an efficient analysis, whereas previous approaches have been unable to handle power grids of such size.

Presents a new approach for the estimation and optimization of standby power dissipation in large MOS digital circuits. We introduce a new approach for accurate and efficient calculation of the average standby or leakage current in large digital circuits by introducing the concepts of "dominant leakage states" and the use of state probabilities. Combined with graph reduction techniques and simplified nonlinear simulation, the method achieves speedups of three to four orders of magnitude over exhaustive SPICE simulations while maintaining very good accuracy. The leakage current calculation is then utilized in a new leakage and performance optimization algorithm for circuits using dual V/sub t/ processes. The approach is the first to consider the assignment of both the V/sub t/ and the width of a transistor, simultaneously. The optimization approach uses incremental calculation of leakage and performance sensitivities and can take into account a partially defined circuit state constraint for the standby mode of the device.

Article Share on On the interaction of power distribution network with substrate Authors: Rajendran Panda Motorola, Inc., Austin, TX Motorola, Inc., Austin, TXView Profile , Savithri Sundareswaran Motorola, Inc., Austin, TX Motorola, Inc., Austin, TXView Profile , David Blaauw Motorola, Inc., Austin, TX Motorola, Inc., Austin, TXView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001Pages 388–393https://doi.org/10.1145/383082.383188Published:06 August 2001Publication History 12citation288DownloadsMetricsTotal Citations12Total Downloads288Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

We present a new method for removing user-specified false subgraphs from timing analysis and circuit optimization. Given a timing graph and a list of specified false paths, false subpaths, or false subgraphs, we generate a new timing graph in which all specified false paths are removed using a process of node splitting and edge removal. We present the necessary and sufficient condition for splitting a node, and show that the number of nodes that must be added to the timing graph is linear with the size of the false path specification. We also present an algorithm for finding the minimum set of nodes that must be split. Since this algorithm requires exponential run time for false subpaths and false subgraphs, we present a heuristic splitting approach which has linear worst-case run time, and where the number of added nodes is linear with the size of the false path specification. The heuristic approach was implemented and results are given for large industrial circuits.

We present a novel approach to compress current signatures for IR-drop analysis of large power grids. Our approach divides the original current signature into error bounded compression sets. Each compression set has a representative timepoint. The compressed current signature consists of the representative timepoints. The compression technique exploits the pattern of change of individual currents, time locality and periodicity to achieve very high quality results. We provide error guarantees for the compression. Our results are superior in compression and accuracy in comparison to other compression methods such as the single cycle compression.

With operating frequencies approaching the gigahertz range, inductance is becoming an increasingly important consideration in the design and analysis of on-chip interconnect. We present an accurate technique for modeling and analyzing the effects of parasitic inductance on power grid noise, signal delay and crosstalk. We propose a detailed circuit model composed of interconnect resistance, inductance and distributed capacitance, device decoupling capacitances, quiescent activity in the grid, pad locations, and pad/package inductance which accurately determines current distribution and, hence, on-chip inductive effects, and proves superior to the traditional simplified loop inductance approach. The model uses partial inductances, computed using an analytical formula for a pair of parallel rectangular conductors spaced in any relative position. We present experimental results, obtained from simulations of industrial circuits, that show the importance of various model components while analyzing on-chip inductance. We also propose a simple sparsification technique to handle large, dense partial inductance matrices.

Careful design and verification of the power distribution network of a chip are of critical importance to ensure its reliable performance. With the increasing number of transistors on a chip, the size of the power network has grown so large as to make the verification task very challenging. The available computational power and memory resources impose limitations on the size of networks that can be analyzed using currently known techniques. Many of today's designs have power networks that are too large to be analyzed in the traditional way as flat networks. In this paper, we propose a hierarchical analysis technique to overcome the aforesaid capacity limitation. We present a new technique for analyzing a power grid using macromodels that are created for a set of partitions of the grid. Efficient numerical techniques for the computation and sparsification of the port admittance matrices of the macromodels are presented. A novel sparsification technique using a 0-1 integer linear programming formulation is proposed to achieve superior sparsification for a specified error. The run-time and memory efficiency of the proposed method are illustrated through the analysis of case studies of several multi-million node power grids, extracted from real microprocessor and DSP designs.

With operating frequencies approaching the gigahertz range, inductance is becoming an increasingly important consideration in the design and analysis of on-chip interconnect. We present an accurate technique for modeling and analyzing the effects of parasitic inductance on power grid noise, signal delay and crosstalk. We propose a detailed circuit model composed of interconnect resistance, inductance and distributed capacitance, device decoupling capacitances, quiescent activity in the grid, pad locations, and pad/package inductance which accurately determines current distribution and, hence, on-chip inductive effects, and proves superior to the traditional simplified loop inductance approach. The model uses partial inductances, computed using an analytical formula for a pair of parallel rectangular conductors spaced in any relative position. We present experimental results, obtained from simulations of industrial circuits, that show the importance of various model components while analyzing on-chip inductance.

Static timing analysis has traditionally used the PERT method for identifying the critical path of a digital circuit. Due to the influence of the slope of a signal at a particular node on the subsequent path delay, an earlier signal with a signal slope greater than the slope of the later signal may result in a greater delay. Therefore, the traditional method for timing analysis may identify the incorrect critical path and report an optimistic delay for the circuit. We show that the circuit delay calculated using the traditional method is a discontinuous function with respect to transistor and gate sizes, posing a severe problem for circuit optimization methods. We propose a new timing analysis algorithm which resolves both these issues. The proposed algorithm selectively propagates multiple signals through each timing edge in cases where there exists ambiguity regarding which arriving signal represents the critical path. The algorithm for propagating the corresponding required times is also presented. We prove that the proposed algorithm identifies a circuit's true critical path, where the traditional timing analysis method may not. We also show that under this method circuit delay and node slack are continuous functions with respect to a circuit's transistor and gate sizes. In addition, we present a heuristic method which reduces the number of signals to be propagated at the expense of a slight loss in accuracy. Finally, we show how the proposed algorithm was efficiently implemented in an industrial static timing analysis and optimization tool, and present results for a number of industrial circuits. Our results show that the traditional timing analysis method underestimates the circuit delay by as much as 38%, while that the proposed method efficiently finds the correct circuit delay with only a slight increase in run time.

We present new modeling and simulation techniques to improve the accuracy and efficiency of transient analysis of large power dis?tribution grids. These include an accurate model for the inherent decoupling capacitance of non-switching devices, as well as a sta?tistical switching current model for the switching devices. More?over, three new simulation techniques are presented for problem size-reduction and speed-up. Results of application of these tech?niques on three PowerPCtmmicroprocessors are also presented.

We present a new approach for estimation and optimization of the average stand-by power dissipation in large MOS digital circuits.To overcome the complexity of state dependence in average leakage estimation, we introduce the concept of "dominant leakage states" and use state probabilities.Our method achieves speed-ups of 3 to 4 orders of magnitude over exhaustive SPICE simulations while maintaining accuracies within 9% of SPICE.This accurate estimation is used in a new sensitivity-based leakage and performance optimization approach for circuits using dual V t processes.In tests on a variety of industrial circuits, this approach was able to obtain 81-100% of the performance achievable with all low V t transistors, but with 1/3 to 1/6 the stand-by current.

We present a methodology for the design and analysis of power grids in the PowerPC™ microprocessors. The methodology covers the need for power grid analysis across all stages of the design process. A case study showing the application of this methodology to the PowerPC™ 750 microprocessor is presented.

A novel technique to explore the performance vs design effort trade-off is proposed. Starting from an optimally synthesized design, performance-critical cells are incrementally and optimally selected and custom-sized to generate this trade-off. Efficient algorithms for the optimal selection, and for improving the reuse of custom-sized cells in the design are given. Significant performance gains are shown in several real circuits through the addition of very few customized cells.

We describe a fast (linear time) procedure to optimally size transistors in a chain of multi-input gates/stages. The fast sizing is used in a simultaneous sizing and restructuring optimization procedure, to accurately predict relative optimal performance of alternative circuit structures for a given total area. The idea extends the concept of optimally sizing a buffer chain and uses tapering constants based on the position of a stage in a circuit, and the position of a transistor in a stack.

Power management is an increasing concern for processor design. In this paper, we presented an overview of traditional power simulation tools and discussed two emerging power management design technologies: power distribution integrity analysis and standby current measurement and optimization. We present methods for accurate peak current simulation, which is needed for power grid integrity analysis, and discuss the generation and compression of the simulation vectors. Also, static approaches for calculating an upper-bound on the maximum peak current are presented. Standby leakage current is state dependent and we present methods for calculating both the average and maximum leakage current. Finally, optimization methods for minimizing the leakage current by either assigning a standby state to the circuit or by using a dual-Vt process are discussed.

We propose a methodology for applying gate-level logictransformations to optimize power in digital circuits.Statisticallysimulated switching information, gate delays,signal arrival patterns, and signal probabilities are consideredin reducing the switching activity-capacitance products.Power reduction up to 45.4% (acerage 12.4%) is achieved,with considerable improvements in area and delay, in pre-optimizedbenchamarks.Also the effect of transformationson the random pattern testability of the circuits is studied.

Traditional synthesis techniques optimize CMOS circuits in two phases: i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in the library are chosen to yield good synthesis results over many blocks or even for an entire chip. Consequently this approach precludes an optimal design of individual blocks which may need custom structures. The authors present a new transistor level technique that optimizes CMOS circuits both structurally and size-wise. The technique is independent of a library and hence can explore a design space much larger than that possible due to gate level optimization. Results demonstrate a significant improvement in circuit performance of the resynthesized circuits.