This article presents a Single-Photon Avalanche Diode (SPAD)-based LiDAR sensor featuring a low-resource time-of-flight (ToF) extraction architecture with robust background-light suppression. The proposed ToF extraction architecture integrates a first effective event detection (FEED) circuit, a shared histogram accumulation circuit, and an address-event representation (AER)-based peak detection circuit. The FEED circuit employs a tunable firing threshold (Fire${}_{\mathrm {th}}$) to suppress background-induced false triggers, and determines whether the shared histogram circuit should operate in first-event or last-event mode. An artificial neural network (ANN) is trained to optimize Firethunder varying background and ranging conditions. The shared histogram architecture exploits the complementary histogram characteristics of the two modes to store the histogram results of two pixel groups in a single shared RAM, thereby improving memory utilization while enabling adaptive exposure control to avoid redundant accumulations. Experimental results demonstrate operation under up to 100 klux background light intensity, a maximum ranging distance of 46 m, and a maximum non-linearity of 0.13 m.

A resource-efficient readout integrated circuit (ROIC) optimized for single-photon avalanche diode (SPAD) array has been implemented in 180 nm CMOS technology to enable high-precision depth sensing. A synchronous-sampling-based iterative candidate histogram circuit is proposed, which leverages photon-trigger correlation analysis to significantly reduce memory consumption, requiring only 90 bits of memory per pixel. An extremum-tracking circuit is employed to enhance the noise suppression capability of the iterative candidate histogram by identifying trigger timestamps with the maximum photon counts within each exposure cycle. To achieve sub-nanosecond range accuracy, a multi-phase synchronous sampling circuit combined with a differential fitting algorithm is employed. A macro-pixel reconstruction circuit is employed to enable adaptive imaging resolution, supporting configurable modes of$160\times 120$,$40\times 40$, and$20\times 20$. The core power of the ROIC is 14.36 mW. To evaluate the ranging performance of the ROIC, a SPAD-based LiDAR prototype is implemented, incorporating a$320\times 240$SPAD array. Experimental results demonstrate that the ROIC achieves 1.8 cm ranging precision with over 90 % measurement success rate within a 30 m detection range and 30 klux background illumination.

This paper presents an image sensor system based on single-photon avalanche diode (SPAD) utilizing a hybrid time-of-flight (ToF) method, which achieves an imaging resolution of$64\times 128$based on a hybrid scanning system. The primary components of the image sensor system include a$16\times 8$SPADs array fabricated using 130nm CMOS technology, along with 128 passive quenching circuits and 128 pulse shaping circuits within the pixels, a digital signal processing (DSP) circuit implemented on the FPGA, and a laser driving circuit with adjustable pulse width. The laser pulse width can be adaptively modified according to the bin size of the partial histogram, thereby improving the signal-to-background light ratio (SBR) and reducing measurement jitter. The DSP incorporates a hybrid partial histogram (HPH) algorithm based on both direct time-of-flight (DToF) and indirect time-of-flight (IToF), along with a non-linear spatiotemporal coincidence detection (NSCD) circuit. The proposed HPH algorithm significantly reduces the storage resource requirements for histograms, eliminating the need for in-pixel time-to-digital converter (TDC). Each pixel’s histogram requires only 180 bits of storage resource. Moreover, the IToF algorithm effectively enhances the system’s measurement precision. The NSCD significantly improves the sensor’s background noise suppression and weak echo detection capabilities. Experimental results indicate that, under a background light intensity of 60 Klux, the image sensor can measure distances up to 60 m, with a measurement precision less than 1 cm.

This paper reports a dual-mode analog counter for Single Photon Avalanche Diode (SPAD)-based image sensors. With the proposed comparator feedback scheme, the precise counting step size configuration is achieved. Cascade counting mode and up/down counting mode are also supported. Additionally, a successive approximation (SA) type calibration method is also proposed to enhance the process, voltage, temperature (PVT) robustness of up/down counting step. With the calibration method, the analog counter in up/down counting mode supports adjusting the step of arrayed analog counters with a master-slave approach and this functionality has been validated through four slave counters. This dual-mode analog counter is fabricated in 180-nm CMOS process and primarily comprises two counting modules (up and down). In each counting module: the dynamic range is 10 bits with the step of 1.3 mV, the area is 79.25 μm2without storage capacitor, and the power consumption is 108.3 nW. The area of SA calibration circuit and four slave-counters is about 350 μm × 255 μm.

This paper proposed a fully integrate single photon ranging system (ISPRS), which mainly consists of a laser pulse driver circuit with adaptive power adjustment, bias voltage generation circuit, 512 independently enabled single photon avalanche diodes (SPADs) used as Reference SPAD array and Return SPAD array respectively, two multi-event time-to-digital converters (TDCs) based on multi-phase sampling, and the ranging extraction circuit. The ranging extraction circuit mainly consists of nonlinear histogram, the FIR with adaptively coefficient adjustment algorithm, and receiving photon adaptive conditioning circuit. The nonlinear histogram is proposed to collect the distribution characteristics of the photons received by the Reference SPAD array and Return SPAD array, which can enhance the equivalent trigger probability of the SPAD array for laser echo. The coefficients of the FIR filter are obtained by normalizing the histogram collected by the Reference SPAD array. By adjusting the number of the enabled SPADs of Reference SPAD array, the envelope of the histogram collected by Reference SPAD array will be changed to match different measurement signal-to-background noise ratio (SBR) for Return SPAD array, which can improve the measurement precision of the ISPRS. The laser power meets the safety of the human eye while effectively improving the measurement range based on the proposed ranging extraction circuit and receiving photon adaptive conditioning circuit. The experimental results show that the measurement range and precision can reach 4.7 m and ±0.5 cm respectively of the ISPRS when the measurement rate is set 30 Hz.

An analog silicon photomultiplier (SiPM) based receiver with wideband transimpedance amplifier (TIA) is proposed for direct ToF LiDAR applications. The analog SiPM comprises a$16\times 32$single photon avalanche diodes (SPADs) array with a 25% fill factor. A fully differential pixel readout circuit is proposed within the pixel cell to facilitate the monolithic integration with the subsequent TIA and reduce the output capacitance of the analog SiPM. The TIA with the multipath feedforward compensation technique is proposed to improve the stability and achieve a wider −3-dB bandwidth. The adder array is used in this design to output the intensity information for the walk error compensation and the target identification. The proposed receiver, which is fabricated in$0.18~\mu \text{m}$HV-CMOS technology, achieves a −3-dB bandwidth of 420 MHz. A maximum detection range of 65 m is obtained with 20 W laser peak power,$1.8^{\circ }\times 1.8^{\circ }$field of view, and 40 mm aperture. A ranging accuracy of ±0.4 cm and precision of 4.5 cm are attained under a condition of 5 klux ambient light based on 1000 measurement results.

This article introduces a pulsed laser direct time-of-flight (dTOF) flash light detection and ranging (LiDAR) sensor fabricated in 0.18-$\mu \text{m}$HV CMOS technology. The chip includes$32\times 32$macro pixels and 1024 time-to-digital converters (TDCs). A noise filtering circuit with different threshold ($\text{N}_{\mathrm {th}}$) configuration is adopted in each macro pixel [formed by four single-photon avalanche diodes (SPADs)], which can suppress strong background light (BG) induced pile-up. To verify the imaging function and effectiveness of the noise filtering circuit, two systems are implemented (System1 for indoor imaging measurement and System2 for outdoor distance measurement). With the help of the noise filtering circuit and a reasonable signal-to-background noise ratio (SBR), the maximum detection range outdoors with reasonable accuracy can be greatly extended (from 12m @ Nth= 1 of System2 to more than 20m @ Nth= 2 of System2 under 70klux of background noise). The counter in the noise filtering circuit can be reused to get intensity information. A robust 13-bit TDC with a reliable reset is introduced. Thanks to a dedicated START/STOP logic and a Schmitt trigger, large TDC quantization errors can be avoided. It achieves a 200ps resolution (LSB) and exhibits an INLp-pof 3.55LSB and a DNLp-pof 0.53LSB. The maximum inter-frame rate can reach 270kfps with 16 IOs operating at speed of 500MHz. Combining 9k inter-frames to get one frame, a frame rate of 30 is achieved for an indoor 3-D imaging. For outdoor measurement, more laser pulses should be accumulated.

This article describes a small footprint, low power gated voltage-controlled ring oscillator (VCRO)-based Time-To-Digital converter (TDC) for Flash Light Detection and Ranging (LiDAR) applications. A group of compact local phase interpolators (PIs) are used to improve the resolution, which is highly area-saving and compatible with in-pixel TDC structure. A non-reset operation mode is introduced to increase the linearity by taking advantage of the dynamic element matching (DEM) property. The proposed TDC has been fabricated in a 0.18-$\mu \text{m}$HV-CMOS technology in a 32$\times32$array, achieving a resolution of 50 ps. A Phase Lock Loop (PLL) is adopted to track the process, voltage, and temperature (PVT) variations and make the resolution tunable. A power-saving analog buffer is used to distribute the stable control voltage to all the in-pixel TDCs. Measurements show a good linearity performance and array uniformity (a deviation of only 0.89 ps), making it suitable for Flash LiDAR applications.

This article presents a 16-channel analog silicon photomultiplier (SiPM) with on-chip front-end for direct time-of-flight (D-ToF) LiDAR applications. The proposed receiver is mainly composed of 16-channel SiPM, variable gain amplifier (VGA) and time-to-digital converter (TDC). Each SiPM channel consists of 256 microcells, and their outputs are connected to a common output terminal in parallel. A novel active quenching circuit is adopted to reduce the long exponential tail in conventional SiPM and enable the capability of multi-echo detection. Current steering circuits are adopted within microcells to make the output current of SiPM immune to SPAD gain variations. The receiver was fabricated in 180-nm HV CMOS technology and integrated into the 16-line LiDAR prototype with optical components. Measurement results show that the sensor is capable of 20 m range imaging with 3 cm accuracy under 40 klux background light conditions. With the mechanical scanning system, a high-resolution image ($240\times16$) can be obtained.

To increase the light detection and ranging (LiDAR) system spatial resolution, the multiple photodetectors are typically deployed in the receiver. An equivalent linear-array receiver with multiplexing operation scheme is presented for the direct time of flight (dToF) LiDAR applications. In particular, the analog front-end (AFE) circuit of the proposed receiver mainly consists of eight transimpedance preamplifiers (preTIAs), a dummy preTIA, a post amplifier (PA) with an 8-to-1 multiplexer, an analog output buffer and a timing discriminator. The proposed AFE circuit, which achieves a transimpedance gain of ~106 dB$\Omega $, a bandwidth of ~220 MHz, an equivalent input-referred noise current of ~5.1 pA/Hz0.5 and a channel switchover time of 6 ns, was fabricated in a 65 nm standard CMOS technology. The associated DC power consumption is 137 mW with a power supply of 2.5 V. The total area of the proposed AFE circuit, which includes the circuit core, bias circuits and I/O PADs, is approximately equal to$1.2\times 1.2$mm2.