Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultradeep submicrometer processes. We characterize the cycle-averaged power model for interconnects accounting for switching statistics and dynamic behaviors. For the sake of signal integrity, cross-coupling effects are also characterized, which reflect logical correlation between adjacent wires. Based on the new models for interconnect power and capacitive crosstalk, we optimize the coupling power consumed by interconnects with crosstalk constraints. Experimental results show that optimized designs save the power consumption about 14% on average.

Based on the new concept of crosstalk immunity set (CIS), procedures to minimize capacitive cross-coupling effects are developed for domino logic circuit. The nets in a crosstalk immunity set are free from crosstalk effects for any combination of input vectors. New algorithms for CIS identification and minimization are proposed to maximize the chance of crosstalk minimization in routing step. Our routing algorithm augmented with CIS information searches for optimal solution to minimize maximum crosstalk the circuit would experience. Experimental results show that the reduction of maximum crosstalk is up to 30% with CIS-augmented routing.

Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultra deep sub-micron processes. We characterize the cycle-averaged power model for interconnects accounting for switching statistics and dynamic behaviors. For the sake of signal integrity, cross-coupling effects are also characterized which reflect logical correlation between adjacent wires. Based on the new models for interconnect power and capacitive crosstalk, we optimize the coupling power consumed by interconnects with crosstalk constraints. Experimental results show that optimized designs save the power consumption significantly.

High performance circuit techniques such as domino logic have migrated from the microprocessor world into more mainstream ASIC designs.The problem is that domino logic comes at a heavy cost in terms of total power dissipation.For mobile and portable devices such as laptops and cellular phones, a high power dissipation is an unacceptable price to pay for high performance.Hence, we study synthesis techniques that allow designers to take advantage of the speed of domino circuits while at the same time to minimize total power consumption.Specifically, in this paper we present three results related to automated phase assignment for the synthesis of low power domino circuits: (1) We demonstrate that the choice of phase assignment at the primary outputs of a circuit can significantly impact power dissipation in the domino block ( 2) We propose a method for efficiently estimating power dissipation in a domino circuit and (3) We apply the method to determine a phase assignment that minimizes power consumption in the final circuit implementation.Preliminary experimental results on a mixture of public domain benchmarks and real industry circuits show potential power savings as high as 34% over the minimum area realization of the logic.Furthermore, the low power synthesized circuits still meet timing constraints.

Till now most efforts in low power lo gic synthesis have oncentr ated on minimizing the total switching activity of a circuit under a zero delay model. This simplification ignor es the effe cts of glitch tr ansitions which may contribute as much as 30% of the total power c onsumption of a circuit. Hence, low power logic synthesis techniques which optimize power under a zer o delay model ar e often not successful in attaining “r eal” p ower savings as measured under a more accurate gener al delay model. In pr actice, to ac curately estimate the switching activity in a circuit under a gener al delay model can be computationally expensive. Hence, to repeatedly call accurate but slow power estimation tools to dir ect the synthesis flow is not a viable approach in the design of low power synthesis tools. In this pap er we take advantage of a fast method for estimating the total switching activity in a circuit under a general delay model to synthesize low power circuits. Sp ecific ally,we use the appr oximation as a basis for algorithms that solve two problems: (1) low power te chnolo gy decomposition of gates under a gener al delay model (2) low power r etiming of sequential cir cuits under a general delay model.

An abundance of research efforts in low power logic synthesis have so far been focused on AND/OR or NAND/NOR based logic. A typical approach is to first generate an initial multi level AND/OR or NAND/NOR representation of a Boolean function. Next, the representation, is optimized in terms of power. However, there are major classes of circuits such as arithmetic functions which have sizable AND/OR representations but have very compact AND/XOR representations. For these functions, the AND/OR based optimization approach often yields poor results. We propose a paradigm for low power logic synthesis based on AND/XOR representations of Boolean functions. Specifically, we propose transforming a Boolean function into a Fixed Polarity Reed Muller form that allows us to efficiently synthesize XOR trees and AND trees with provably minimum switching activity. Preliminary experimental results show that we attain good power savings with negligible area overhead and often area reduction when compared to conventional AND/XOR based synthesis methods and the Berkeley SIS system.

The advent of poTtable digital devices such as laptop peTsona1 computers has made low poweT ciTcuit design an incTeasingly impoTtant TeseaTch area.Recently, low power decomposition foT simple logic gates such as AND and OR has been extensively Teseazhed.HoweveT, the pToblem of MUX decomposition to minimize poweT dissipation has not been addTessed.In this papeT, we study the pToblem of low power multiplexer (MUX) decomposition.MUX decomposition is the procedure of tTansfo?ming an n-to-one MUX into an equivalent tTee of two-to-one MUXes.We propose a formulation for the minimum power MUX decomposition problem based on the common CMOS pass tTan-sistoT implementation of a MUX.Given the occuTTence pTobabilities of the data signals and theiT on probabilities, we analyze the poweT dissipation of OUT MUX implementation and give a geneTa1 method for computing the poweT dissipation of a MUX tTee decomposition.We then present seveTa1 algorithms which eficientiy generate minimum power MUX decompositiotas.We demon&ate the effectiveness of OUT algoTi&ns wi& experimental Tesults.