A photonic packet switching communication network is presented and its feasibility is discussed. In particular, it is explicitly supposed that the electro-optical conversion is done only by the end users, while all other network functions (transmission, signal processing, routing, etc.) are implemented by photonic circuits. To interconnect the independent channels obtained by partitioning the global optical bandwidth, the class of topologies, called extended shufflenet, is considered. Two particular networks of this class (multiwavelength loop and extended shufflenet with shared channels), which have routing algorithms simple enough to be implemented by photonic circuits, have been analyzed. The photonic architecture developed for the multiwavelength loop has been applied to the extended shufflenet, which is a feasible possibility for a network with a sustained capacity of the order of the gigabit/s per user. The photonic components used in these circuits have been demonstrated in various laboratories and essentially comprehend delay lines, optical switches, simple optical gates, frequency converters, optical filters, etc. Some of these components have been experimentally integrated in subsystems and the implementation of the proposed circuit with today technology appears feasible.>

The author proposes a three-state image model whose elements are named object, background, and new-scene after their representation of the corresponding structural situation. An interframe state transition diagram controlled by luminance differences is introduced. The model is then utilized in a background luminance updating algorithm based on a maximum a posteriori probability. Applications of the model and the updating algorithm in predictive video coding at low bit rate (64 kb/s and less) are suggested.>

This paper proposes a hierarchical representation of digital signal processing algorithms suitable for real-time implementations. Petri net models are used to demonstrate every possible operating parallelism in their graphical expression, the marked Petri graph. Moreover, a hierarchical algorithm execution control based on delayed Petri graphs is presented. A strictly modular system architecture suitable for VLSI implementation and data-driven processing is reviewed in its main components. The algorithm representation is then applied to the design of the control part of the system modules. Details at the logic level of the controllers for an array of digital signal processors are presented as an application of the proposed methodology.