The recent research efforts in smart grids and residential power management are oriented to monitor pervasively the power consumption of appliances in domestic and non-domestic buildings. Knowing the status of a residential grid is fundamental to keep high reliability levels while real time monitoring of electric appliances is important to minimize power waste in buildings and to lower the overall energy cost. Wireless Sensor Networks (WSNs) are a key enabling technology for this application field because they consist of low-power, non-invasive and cost-effective intelligent sensor devices. We present a wireless current sensor node (WCSN) for measuring the current drawn by single appliances. The node can self-sustain its operations by harvesting energy from the monitored current. Two AAA batteries are used only as secondary power supply to guarantee a fast start-up of the system. An active ORing subsystem selects automatically the suitable power source, minimizing power losses typical of the classic diode configuration. The node harvests energy when the power consumed by the device under measurement is in the range 10W÷10kW, which also corresponds to the range of current 50mA÷50A drawn directly from the main. Finally the node features a low-power, 32-bit microcontroller for data processing and a wireless transceiver to send data via the IEEE 802.15.4 standard protocol.

Data reduction strategy is one of the schemes employed to extend network lifetime. In this paper we present an implementation of a light-weight forecasting algorithm for sensed data which saves packet transmission in the network. The proposed Naive algorithm achieves high energy savings with a limited computational overhead on a node. Simulation results from realistic Building monitoring application of WSN are compared with well-known prediction algorithms such as ARIMA, LMS and WMA models. We implemented a real-world deployment using 32bit mote-class device. Overall, up to 96% transmission reduction is achieved using our Naive method, while still able to maintain a considerable level of accuracy at 0.5°C error bound and it is comparable in performance to the more complex models such as ARIMA, LMS and WMA.

Data reduction strategy is one of the schemes employed to extend network lifetime. In this paper we present an implementation of a light-weight forecasting algorithm for sensed data which saves packet transmission in the network. The proposed Naive algorithm achieves high energy savings with a limited computational overhead on a node. Simulation results from realistic Building monitoring application of WSN are compared with well-known prediction algorithms such as ARIMA, LMS and WMA models. We implemented a real-world deployment using 32bit mote-class device. Overall, up to 96% transmission reduction is achieved using our Naive method, while still able to maintain a considerable level of accuracy at 0.5 °C error bound and it is comparable in performance to the more complex models such as ARIMA, LMS and WMA.

Adaptive body bias (ABB) and adaptive supply voltage (ASV) have been showed to be effective methods for post-silicon tuning of circuit properties to reduce variability. While their properties have been compared on generic combinational circuits or microprocessor circuit sub-blocks, the advent of multi-core systems is bringing a new application domain forefront. Global interconnects are evolving to complex communication channels with drivers and receivers, in an attempt to mitigate the effects of reverse scaling and reduce power. The characterization of the performance spread of these links and the exploration of effective and power-aware compensation techniques for them is becoming a key design issue. This work compares the variability compensation efficiency of ABB vs ASV when put at work in two representative link architectures of today's ICs: a traditional full-swing interconnect and a low-swing signaling scheme for low-power communication. We provide guidelines for the post-silicon variability compensation of these communication channels.

Ultra low power digital systems are key for any future wireless sensor nodes but also inside nomadic embedded systems (such as inside the digital front end of software defined radios). These systems require the highest possible energy efficiency of logic, which can only be achieved by operating in moderate inversion. Unfortunately, when operating near the threshold voltage, transistors become highly sensitive to process variations, thereby increasing leakage currents and complicating timing closure. Rather than pursuing a worst-case design approach for dealing with these uncertainties, we present a hybrid self-timed/synchronous approach. It will be demonstrated on the VEX VLIW core designed for ultra low-power operations. Experimental results of our approach demonstrate performance benefits up to 2times and significant energy savings at low throughput rates.

Hardware for ambient intelligence needs to achieve extremely high computational efficiency (up to 40GOPS/W). An important way for reaching this is exploiting parallelism, and more specifically data-level parallelism enabled by SIMD. Whereas a large body of research exists on the benefits of the architectural design of and compilation onto SIMD, the design of energy-optimal functional units for SIMD has received limited attention. It appears that existing SIMD functional units are designed in an area optimal, but not energy optimal way. By exploiting the difference in critical path length for the types of operations (e.g., 4times8/2times16/1times32), SIMD adders can be developed that save up to 40% of energy. In this paper, the authors present these adders, the issues of building them and quantify their benefits for different usage scenarios and operating frequencies.

New tendencies envisage multiprocessor systems-on-chips (MPSoCs) as a promising solution for the consumer electronics market. MPSoCs are complex to design, as they must execute multiple applications (games, video) while meeting additional design constraints (energy consumption, time-to-market). Moreover, the rise of temperature in the die for MPSoCs can seriously affect their final performance and reliability. In this article, we present a new hardware-software emulation framework that allows designers a complete exploration of the thermal behavior of final MPSoC designs early in the design flow. The proposed framework uses FPGA emulation as the key element to model hardware components of the considered MPSoC platform at multimegahertz speeds. It automatically extracts detailed system statistics that are used as input to our software thermal library running in a host computer. This library calculates at runtime the temperature of on-chip components, based on the collected statistics from the emulated system and final floorplan of the MPSoC. This enables fast testing of various thermal management techniques. Our results show speedups of three orders of magnitude compared to cycle-accurate MPSoC simulators.

With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor System-On-Chip (MPSoC) architectures have become widespread. These new systems are complex to design as they must execute multiple complex applications (e.g. video processing, 3D games), while meeting additional design constraints (e.g. energy consumption or time-to-market). Moreover, the rise of temperature in the die for MPSoC components can seriously affect their final performance and reliability. Therefore, mechanisms to efficiently evaluate complete HW/SW MPSoC designs in terms of energy consumption, temperature, performance and other key metrics are needed. In this paper, we present a new HW/SW FPGA-based emulation framework that allows designers to rapidly extract a number of critical statistics from processing cores, memories and interconnection systems being emulated on a FPGA. This information is then used to interact in real-time with a SW thermal model running on a host computer via an Ethernet port. The results show speed-ups of three orders of magnitude compared to cycle-accurate MPSoC simulators, which enable a very fast exploration of a large range of MPSoC design alternatives at the cycle-accurate level. Finally, our HW/SW framework allows designers to test run-time thermal management strategies with real-life inputs without any loss in the performance of the emulated system.

The power density inside high performance systems continues to rise with every process technology generation, thereby increasing the operating temperature and creating "hot spots" on the die. As a result, the performance, reliability and power consumption of the system degrade. To avoid these "hot spots", "temperature-aware" design has become a must. For low-power embedded systems though, it is not clear whether similar thermal problems occur. These systems have very different characteristics from the high performance ones: they consume hundred times less power, they are based on a multi-processor architecture with lots of embedded memory and rely on cheap packaging solutions. In this paper, we investigate the need for temperature- aware design in low-power systems-on-a-chip and provide guidlines to delimit the conditions for which temperature-aware design is needed