A harmonic cancellation technique based on a phase manipulation technique is presented for Ku-band voltage-controlled oscillators (VCO), achieving significant phase noise reduction, especially at the$1/f^{3}$region. The proposed VCO incorporates an auxiliary PMOS transistor with dynamically controlled biasing to generate additional high-order components to compensate for the intrinsic phase difference between the high-order harmonic components of the main PMOS and NMOS cross-coupled transistors, establishing the required$180^{o}$phase difference ($\Delta \theta $) between them. The alignment, facilitated by the proposed technique, significantly suppresses the undesired high-order harmonic components entering the tank’s capacitive path and disturbing its natural frequency. The proposed VCO is fabricated in 65nm CMOS technology, achieving a phase noise of −33.78 dBc/Hz at 1 kHz and -112 dBc/Hz at 1 MHz. The phase noise improvement reaches 5.56 dB at the$1/f^{3}$region compared to a conventional complementary VCO. With a low power consumption of 4.5 mW, the proposed VCO achieves an excellent figure-of-merit (FoM) of −188.4 dBc/Hz with a tuning range of 1.1 GHz (8.1%) operating from 13 GHz to 14.1 GHz.

This paper presents a current-reused coupled oscillator with improved noise circulating technique for phase noise improvement. The proposed current-reused coupled oscillator with order of 2, where the noise circulation oscillator is stacked on top of PMOS cross-coupled oscillator solves the strict trade-off between power consumption and phase noise. The degeneration transistors for noise circulating operations are biased in triode-region instead of in saturation to provide an optimum delay in loop gain, such that the positive and negative phase change in the normalized impulse sensitivity function (ISF) become more symmetric. Thus, the 1/f3phase noise is significantly improved. The voltage-controlled oscillator (VCO) was implemented using CMOS 65nm technology, and the measurement results demonstrated its operation within a frequency range of 15.4–17 GHz (9.8% tuning range). Despite its low power dissipation of 6.3 mW, the VCO design exhibits excellent performance, offering a phase noise of -111.2 dBc/Hz at 1 MHz offset frequency. Furthermore, the proposed VCO attains a figure of merit (FoM) of -187.4 dBc/Hz.

A dynamic voltage scaling (DVS) enabled distributed digital low-dropout voltage regulator (LDO) is described. The proposed distributed LDO utilizes a multi-point average sensing to enable rapid and uniform output voltage regulation across a large-scale power grid, even during unbalanced load transients. A 16-bit thermometer-code flash analog-to-digital converter (FADC) combined with unary passgate configurations and an adaptive on-resistance (R$_{\mathrm {ON}}$) modulation is employed to ensure a small output voltage ripple during DVS operation, using only a small 13.4nF output capacitor. The proposed distributed LDO has been implemented in 28nm CMOS, achieves a 10.4A/mm2 current density, 99.96% current efficiency, and a 20.1ps FOM. It has also been tested under various unbalanced load transient conditions and can rapidly regulate the output voltage back to the target level.

This paper presents an inductor-less, low-power, wideband, and noise-cancelling low-noise amplifier (LNA) for simultaneous deployment in low-power and multi-standard applications. The main novelty of this work lies in the concurrent utilization of the feedforward and feedback techniques to achieve simultaneous noise and distortion cancellation of input CG stage and bandwidth extension while maintaining low-power input matching, respectively. The proposed LNA is analyzed using the two-port network theory, thereby highly simplifying the extraction of device parameters and evaluating optimum design conditions. The proposed LNA is fabricated in a standard 65-nm CMOS process and occupies a core area of only 0.011-mm$^2$while consuming 960-$\mu$W of dc power from a 0.78-V supply. The peak$S_{21}$of LNA is 15.6 dB with a higher cut-off bandwidth ($BW_{-3dB}$) of 4.2 GHz. The minimum NF of LNA is 4.45 dB at 2 GHz, while the measuredIIP$_3$of the LNA is -16 dBm at the same frequency. Based on the measured data, the proposed LNA provides the widest bandwidth among the works reported in the low-power, inductor-less regime along with one of the highestFOM$_{I}$and a competitiveFOM$_{II}$.

This article presents the frequency-locked high-power RF oscillator using a gallium nitride (GaN) high electron mobility transistor (HEMT) amplifier and phase-locked loop (PLL) for 2.4-GHz industrial, scientific, and medical (ISM) band applications. The proposed architecture exploits the GaN power amplifier in the positive-feedback loop, whereas the desired phase shift for the target oscillating frequency is regulated from the PLL. To the best of our knowledge, this work is the first to employ the frequency locking scheme for a high-power solid-state RF oscillator. A detailed analysis of the oscillation conditions and the efficiency is provided. The prototype circuit is implemented with hybrid phase shifters and a fractional- N frequency synthesizer. The implemented RF oscillator circuit operates from 2.3 to 2.575 GHz and achieves a low phase noise of -131.8 dBc/Hz at a 1-MHz offset frequency. The power efficiency of the proposed oscillator reaches 58%, and the PLL incurs only 0.2% efficiency degradation.

This brief presents a low-complexity I/Q (in-phase and quadrature components) imbalance calibration method for the transmitter using quadrature modulation. Impairments in analog quadrature modulator have a deleterious effect on the signal fidelity. Among the critical impairments, I/Q imbalance (gain and phase mismatches) deteriorates the residual sideband performance of the analog quadrature modulator degrading the error vector magnitude. Based on the theoretical mismatch analysis of the quadrature modulator, we propose a low-complexity I/Q imbalance extraction algorithm. After the parameter extraction, the transmitter is calibrated by imposing the counter imbalanced mismatch of the transmitter through the digital baseband. In comparison with existing I/Q imbalance calibration methods, the novelty of the proposed method lies in that: 1) only three spectrum measurements of the device-under-test are needed for extraction and calibration of gain and phase mismatches; 2) due to the blind nature of the calibration algorithm, the proposed approach can be readily applicable to an existing I/Q transmitter; 3) no extra hardware that degrades the calibration accuracy is required; and 4) due to the noniterative nature, the proposed method is faster and computationally more efficient than previously published methods.

A highly-linear I-channel receiver prototype is presented for a 3 to 6 GHz broadband radio system with a 200 MHz baseband bandwidth and verified to operate under congested spectrum environments. A direct conversion receiver developed from this prototype is suitable for a cognitive radio, fifth-generation (5G) receiver, and other wireless systems with a total (in-band signal plus blocker) power above -6.0 dBm. The broadband receiver consists of a low-noise transconductance amplifier, a passive mixer, a wideband transimpedance amplifier and a power-efficient minimally-invasive baseband filter. The low-noise transconductance amplifier with high linearity employs a cross-coupled structure and resistive degeneration to achieve low noise and high linearity simultaneously. The common-gate based LNTA achieves 2.3 dB noise figure in simulation. Fabricated in a mainstream 40 nm CMOS technology, the worst-case measured system noise figure is under 5.8 dB at 3 MHz baseband frequency, and the conversion gain is larger than 12.8 dB with passband variations under 2 dB from 1 MHz up to 200 MHz signal bandwidth. Over 3 to 6 GHz, the receiver's in-band IIP3 and input P1db are higher than 15.1 dBm and 3.0 dBm, respectively, whereas the power consumption varies from 64.1 mW to 69.6 mW.

This brief presents a low-complexity I/Q (in-phase and quadrature components) imbalance calibration method for the transmitter using quadrature modulation. Impairments in analog quadrature modulator have a deleterious effect on the signal fidelity. Among the critical impairments, I/Q imbalance (gain and phase mismatches) deteriorates the residual sideband performance of the analog quadrature modulator degrading the error vector magnitude. Based on the theoretical mismatch analysis of the quadrature modulator, we propose a low-complexity I/Q imbalance extraction algorithm. After the parameter extraction, the transmitter is calibrated by imposing the counter imbalanced mismatch of the transmitter through the digital baseband. In comparison with existing I/Q imbalance calibration methods, the novelty of the proposed method lies in that: 1) only three spectrum measurements of the device-under-test are needed for extraction and calibration of gain and phase mismatches; 2) due to the blind nature of the calibration algorithm, the proposed approach can be readily applicable to an existing I/Q transmitter; 3) no extra hardware that degrades the calibration accuracy is required; and 4) due to the noniterative nature, the proposed method is faster and computationally more efficient than previously published methods.

An integrated ultrahigh-frequency (UHF) receiver is presented. A systematic analysis to quantify the interdependence of baseband filter and analog-to-digital converter (ADC) dynamic range in broadband receivers is presented. This analysis shows that: (1) low-order Butterworth filters are favorable when undesired power is dominated by far out blockers and (2) high-order inverse Chebyshev filters can reduce the resolution of a subsequent ADC by up to two additional bits in the presence of adjacent analog narrowband blockers. Based on the analysis, a cascaded, programmable, hybrid active-RC and switched-capacitor (SC) baseband filter is proposed. An all-digital nonoverlap clock tuning system to minimize the variation of available settling time window in SC circuits is also proposed. The receiver integrates the proposed filter with an RF variable gain amplifier (RFVGA) and a passive mixer. This receiver achieves a measured noise figure of 7.9 dB, an IIP3 of -8 dBm at maximum gain and +2 dBm at 9-dB RF attenuation. The chip consumes 120 mW (RFVGA, mixer and I-channel baseband) from 1.8-V analog/2.5-V digital dual supply and occupies 2.14 mm2in IBM 0.18-μm RF CMOS technology.

This work presents an integrated ultra high frequency (UHF), broadband direct-conversion receiver. The receiver integrates a single-ended RFVGA, an on-chip single-to-differential balun, a current-mode passive mixer, and a combination of continuous and discrete-time baseband filter with built-in anti-aliasing. Targeted to operate between 470-862 MHz, the receiver achieves a noise figure of 7.9dB, an IIP3 of -8dBm at maximum gain and an IIP3 of +2dBm at 9dB RF attenuation. The gain- and frequency-programmable baseband section implements an 8thorder inverse chebyshev low pass approximation achieving >42dB attenuation at an offset of 1.75 MHz for the 4 MHz frequency setting. Overall, the receiver consumes 120mW from 1.8V analog/2.5V digital dual supply and occupies 2.14mm2in IBM 0.18μm RFCMOS technology.