Aberrant alterations in genome copy number, chromatin accessibility, and transcriptional programs all play pivotal roles in cancer. The Numbat algorithm has been widely adopted to perform copy number variation (CNV) inference from single-cell RNA sequencing (scRNA-seq) data. Here, we introduce Numbat-multiome that extends the capabilities of Numbat to perform CNV inference from both scRNA-seq and accessible chromatin profiles (through single-cell Assay of Transposase [Tn5]-Accessible Chromatin sequencing [scATAC-seq] data), either separately or in an integrated manner. Our approach unifies data originating from different modalities through a binning strategy that relies on a common genomic coordinate system across modalities. We demonstrate the tool's robust performance in four running modes (RNA gene, RNA bin, ATAC bin, and Combined bin) using benchmark cohorts of tumors with dynamic changes in expression patterns and copy number heterogeneity, including early-stage multiple myeloma and Richter's syndrome arising from chronic lymphocytic leukemia, validated against whole-genome sequencing. Numbat-multiome achieves high precision and recall (median F1>0.9) across different CNV event types, with consistent performance across sample types and event lengths. The tool's ability to track clonal evolution in serial samples and identify rare subclones allows for integration of epigenomic profiles at the subclonal level, providing new insights into the stepwise genetic and epigenetic changes underlying cancer phenotypic shifts.

The exploration of utilizing reconfigurable circuits with parallel computing capabilities has been conducted to enhance sorting performance and reduce power consumption. However, most sorting algorithms using dedicated processors are based on parallelization designs of serial algorithms without considering the design method of large-scale integrated circuits. This results in various issues, including the overuse of$I/O$interface resources, on-chip storage resources, and complex layout wiring. In this article, we extend the 2-tuple relation in the uniform recurrence equation (URE) structure used to define the systolic array to n-tuples, and the extended structure is flexible in defining$I/O$bandwidth and concurrency. Then we define the multiconcurrency systolic sorter array (MCSSA) algorithm based on the extended URE structure, which has a flexible$4N/n$time complexity based on the n-tuple relation. Moreover, this systolic array can simultaneously sort two independent sequences, increasing the reuse of resources. Afterwards, we encapsulate each n-tuple into a processing element (PE) cell. The entire MCSSA consists of these interconnected PE cells, each of which can be customized in terms of data bit width and type. Last but not least, we have improved the merge tree structure called MC-merge tree. The concurrency of this algorithm can also be flexibly defined, we use this algorithm combined with MCSSA to cope with large-scale sorting scenarios. In our experiments, we have demonstrated the speed-up ratio of MCSSA relative to other state of the art (SOTA) sorting algorithms. Inheriting the unity and simplicity from the Systolic Array architecture, MCSSA achieves a maximum$73.17\times $acceleration ratio on the U200. In addition, the MC-merge tree expands the MCSSA sorting scale with a maximum of 450.56 times while maintaining the advantage of the acceleration ratio. The results of our study demonstrate that MCSSA and MC-merge tree have better acceleration, throughput and scalability advantages over other SOTA algorithms.

The increasingly prevalent livecast streaming causes expensive bandwidth costs and delivery capacity challenges for the content delivery network (CDN) service. As an emerging paradigm, edge computing offers new opportunities to address this issue. The existing works are limited to the data volume pricing model. In contrast, we focus on the 95th-percentile pricing model, which is adopted by many large-scale livecast systems. We propose a Cost-aware Edge-assisted Livecast system (CEL) to minimize the bandwidth cost, consisting of two components: 1) the Shapley values are leveraged to model the actual bandwidth costs for the CDN and edge servers in different time slots, together with acceleration technologies for fast Shapley value estimation and 2) a greedy request scheduling algorithm with theoretical guarantees is proposed to solve the online request scheduling problem, which is NP-hard. Based on real-world data from an operational livecast system, our experiments demonstrate thatCELis time-efficient and achieves at least 14.81% bandwidth cost savings compared with four state-of-the-art methods.

Volumetric videos offer viewers more immersive experiences, enabling a variety of applications. However, state-of-the-art streaming systems still need hundreds of Mbps bandwidth to transmit volumetric videos, exceeding the common bandwidth capabilities of mobile devices. We find a research gap in reusing inter-frame redundant information to reduce bandwidth consumption, while the existing inter-frame compression methods rely on the so-calledexplicit correlation, i.e., the redundancy from the same/adjacent locations in the previous frame, which does not apply to highly dynamic frames or dynamic viewports. This paper introduces a new concept calledimplicit correlation, i.e., the consistency of topological structures, which stably exists in dynamic frames and is beneficial for reducing bandwidth consumption. We design a mobile volumetric video streaming system Hermes consisting of an implicit correlation encoder to reduce bandwidth consumption and a hybrid streaming method that adapts to dynamic viewports. Experiments on public datasets show that Hermes achieves a frame rate of 30+ FPS over daily networks and on commodity smartphones, with at least 3.64× and 3.34× improvement compared with two state-of-the-art baselines, respectively.

The business growth of live streaming causes expensive bandwidth costs from the Content Delivery Network service. It necessitates traffic adaptation, i.e., adapting video bitrates for cost-efficient bandwidth utilization, especially under the 95$^{\rm \textit {th}}$percentile pricing. However, our data-driven investigations indicate the existing methods are hard to achieve bitrate-cost balance in a long month-level billing cycle due to dynamic traffic patterns. We propose TrafAda, a learning-based cost-aware traffic adaptation method consisting of i) an ultra-long-term bandwidth demand forecasting model to learn complex bandwidth usage patterns, and ii) an imitation learning-based bitrate decision mechanism to optimize the ultra-long-term objective. We have implemented and deployed TrafAda on a large-scale live streaming system in China serving over one billion viewers from 388 cities. The results show that TrafAda improves peak-hour bitrate, quality of experience (QoE), and watching time by 34.75%, 44.56%, and 10.68%, respectively, without extra bandwidth cost, which can be converted to a considerable value for a commercial system.

The use of reconfigurable circuits with parallel computing capabilities has been explored to enhance sorting performance and reduce power consumption. Nonetheless, most sorting algorithms utilizing dedicated processors are designed solely based on the parallelization of the algorithm, lacking considerations of specialized hardware structures. This leads to problems, including but not limited to the consumption of excessive I/O interface resources, on-chip storage resources, and complex layout wiring. In this paper, we propose a Systolic Sorter Array, implemented by a Uniform Recurrence Equation (URE) with highly parameterised in terms of data size, bit width and type. Leveraging this uniformly recursive structure, the sorter can simultaneously sort two independent sequences. In addition, we implemented global and local control modes on the FPGA to achieve higher computational frequencies. In our experiments, we have demonstrated the speed-up ratio of SSA relative to other state of the art (SOTA) sorting algorithms using C++$std$::$sort()$as benchmark. Inheriting the benefits from the Systolic Array architecture, the SSA reaches up to 810 Mhz computing frequency on the U200. The results of our study show that SSA outperforms other sorting algorithms in terms of throughput, speed-up ratio, and computation frequency.

Volumetric videos offer viewers more immersive experiences, enabling a variety of applications. However, state-of-the-art streaming systems still need hundreds of Mbps, exceeding the common bandwidth capabilities of mobile devices. We find a research gap in reusing inter-frame redundant information to reduce bandwidth consumption, while the existing inter-frame compression methods rely on the so-called explicit correlation, i.e., the redundancy from the same/adjacent locations in the previous frame, which does not apply to highly dynamic frames or dynamic viewports. This work introduces a new concept called implicit correlation, i.e., the consistency of topological structures, which stably exists in dynamic frames and is beneficial for reducing bandwidth consumption. We design a mobile volumetric video streaming system Hermes consisting of an implicit correlation encoder to reduce bandwidth consumption and a hybrid streaming method that adapts to dynamic viewports. Experiments show that Hermes achieves a frame rate of 30+ FPS over daily networks and on commodity smartphones, with at least 3.37x improvement compared with two baselines.

Deep neural networks (DNNs) have been widely used in many cyber–physical systems (CPSs). However, it is still a challenging work to deploy DNNs in real-time systems. In particular, the execution time of DNN inference must be predictable, s.t. it could be known whether the runtime inference can complete within a required timing constraint. Moreover, the timing constraints may change dynamically with the runtime environment in many embedded applications, such as autonomous cars. A possible way to meet such dynamic real-time requirements is to execute different subnetworks of a DNN at runtime. However, improper construction of subnetworks may not only introduce unpredictable inference time, s.t. the real-timing constraints could be violated unexpectedly, but also has poor compatibility with the well-optimized machine learning framework (e.g., TensorFlow). In this article, we study the predictability when executing different subnetworks of a DNN. In particular, we present a featurewise runtime adaptation framework for DNN inference, which is implemented and validated on NVIDIA Jetson TX2 and Nano with TensorFlow. The experimental results show that our method can achieve predictable inference time in comparison with the state-of-the-art methods.

Sorting is essential for many scientific and data processing problems. It is significant to improve the efficiency of sorting. Taking advantage of specialized hardware, parallel sorting, e.g., sorting networks and linear sorters, implements sorting in lower time complexity. However, most of them are designed based on the parallelization of algorithms, lacking consideration of specialized hardware structures. In this article, we propose an extended nonstrict partially ordered set-based configurable linear sorter on field-programmable gate arrays (FPGAs). First, we extend nonstrict partial order to the binary tuple and n-tuple nonstrict partial orders. Then, the linear sorting algorithm is defined based on them, with the consideration of hardware performance. It has 4N/n time complexity varying from 4 to 2 N as the tuple size varies. The number of comparisons reduces to N/2 in binary tuple-based sorting, which is half of the state-of-the-art insertion linear sorting. Finally, we implement the linear sorter on FPGAs. It consists of multiple customizable micro-cores, named sorting units (SUs). The SU packages the storage and comparison of the tuple. All the SUs are connected into a chain with simple communication, which makes the sorter fully configurable in length, bandwidth, and throughput. They also act the same in each clock cycle, so that the achieved frequency of the sorter improves. In our experiment, the sorter achieves at most 660-MHz frequency, 5.6 Gb/s throughput, and 87 times speed-up compared with the quick sort algorithm on general processors.

BACKGROUND: Histopathology images are critical for medical diagnosis, e.g., cancer and its treatment. A standard histopathology slice can be easily scanned at a high resolution of, say, 200,000×200,000 pixels. These high resolution images can make most existing imaging processing tools infeasible or less effective when operated on a single machine with limited memory, disk space and computing power. RESULTS: In this paper, we propose an algorithm tackling this new emerging "big data" problem utilizing parallel computing on High-Performance-Computing (HPC) clusters. Experimental results on a large-scale data set (1318 images at a scale of 10 billion pixels each) demonstrate the efficiency and effectiveness of the proposed algorithm for low-latency real-time applications. CONCLUSIONS: The framework proposed an effective and efficient system for extremely large histopathology image analysis. It is based on the multiple instance learning formulation for weakly-supervised learning for image classification, segmentation and clustering. When a max-margin concept is adopted for different clusters, we obtain further improvement in clustering performance.