A new interleaved high step-up isolated DC-DC converter with zero-voltage switching (ZVS) is proposed in this paper. The configuration is composed of the active clamp circuits and voltage doubler circuits with parallel-input series-output structure. The active clamp circuits are used to achieve ZVS performance for the power switches such that the switching losses are reduced. The voltage doubler circuits are used to obtain high voltage gain. The voltage stresses on the power switches are greatly lower than the output voltage such that the low-voltage-rated MOSFETs with low on-resistances can be adopted to reduce the conduction losses. The input ripple current is reduced by the interleaved operation. The energy stored in leakage inductances of the coupled inductors is recycled to avoid the voltage spike on the main switches. The operating principle and steady-state analysis of the proposed converter are presented in detail. Finally, a 1000 W prototype converter with 36 V input and 380 V output is built and tested in the laboratory. The experimental results are presented to validate the feasibility and the performance of the proposed converter.

This paper presents results on formal verification of high-speed cryptographic software. We consider speed-record-setting hand-optimized assembly software for Curve25519 elliptic-curve key exchange presented by Bernstein et al. at CHES 2011. Two versions for different microarchitectures are available. We successfully verify the core part of the computation, and reproduce detection of a bug in a previously published edition. An SMT solver supporting array and bit-vector theories is used to establish almost all properties. Remaining properties are verified in a proof assistant with simple rewrite tactics. We also exploit the compositionality of Hoare logic to address the scalability issue. Essential differences between both versions of the software are discussed from a formal-verification perspective.