We design and implement an autonomous driving system based on image recognition using programmable SoCs. The proposed system equips two FPGA boards and three cameras. One FPGA board implements a driving control system, and the other FPGA board implements object detection and recognition using machine learning algorithms. Driving control is performed based on road edge line detection and road marking recognition using the canny edge detection. On the other hand, image detection and recognition of traffic lights are implemented using the random forest method with HOG features. In the development framework of programmable SoC of Zynq 7000, we adopt a Hardware/Software co-design to balance the design period and system performance required for real-time processing.

This paper proposes a highly dense reconfigurable architecture that introduces via-switch device, which is a nonvolatile resistive-change switch and is used in crossbar switches. Via-switch is implemented in back-end-of-line layers only, and hence the front-end-of-line (FEoL) layers under the crossbar can be fully exploited for highly dense logic blocks. The proposed architecture uses the FEoL layers for fine-grained lookup tables and coarse-grained arithmetic/memory units for improving performance and compatibility with various applications. A case study of application mapping shows the proposed architecture can reduce the array area by 21.7%, thanks to the bidirectional interconnection. Thanks to F2footprint and one order of magnitude lower resistivity of via-switch compared to MOS switch, the crossbar density is improved by up to 26× and the delay and energy in the interconnection are reduced by 90% and 94% at 0.5-V operation.

This paper proposes a highly-dense reconfigurable architecture that introduces via-switch device, which is a kind of resistive RAM and is used in crossbar switches. Since via-switch is implemented in BEOL layers only, the FEOL layer under the crossbar can be fully exploited for highly-dense logic blocks. The proposed architecture uses the FEOL layer for fine-grained look-up tables and coarse-grained arithmetic/memory units for better performance and highly wide applications. In a case study of application mapping, the proposed architecture reduces array area by 76% thanks to mixed grained logic structure and overlay bidirectional interconnection. Thanks to 18F2footprint and one order of magnitude lower resistivity of via-switch compared to MOS switch, the crossbar density is improved by 26× and the delay and energy in the interconnection are reduced by 90% and 93% at 0.5V operation.

This paper presents a mixed-grained reconfigurable VLSI array architecture that can cover mission-critical applications to consumer products through C-to-array application mapping. A proof-of-concept VLSI chip was fabricated in a 65nm process. Measurement results show that applications on the chip can be working in a harsh radiation environment.

Extreme scaling imposes enormous challenges, such as variability increase and soft-error vulnerability, on the resilience of VLSI circuits and systems. For coping with those threats, we have been developing a VLSI platform that can realize a dependable circuit with required level of reliability. In the platform, circuit-level resilience to variability is achieved by on-chip performance monitoring and variability compensation by localized body biasing. Architecture-level resilience to soft-errors is accommodated by a mixed-grained reconfigurable array in which functionality as well as reliability can be configured. Those properties have been experimentally verified by proof-of-concept chips in 65 nm process. Overview of the variability and soft-error resilience of the platform will be explained, followed by experimental demonstrations.

This paper presents a worst-case-aware design methodology for an oscillator-based true random number generator (TRNG) that produces highly random bit streams even under deterministic noise. We propose a stochastic behavior model to efficiently determine design parameters, and identify a class of deterministic noise under which the randomness gets the worst. They can be used to directly estimate the worst χ value of a poker test under deterministic noise without generating bit streams, which enables efficient exploration of design space and guarantees sufficient randomness in a hostile environment. The proposed model is validated by measuring prototype TRNGs fabricated with a 65-nm CMOS process.

This paper proposes a coarse-grained dynamically reconfigurable architecture that offers flexible reliability to deal with soft errors and aging. The notion of a cluster is introduced as a basic architectural element; each cluster can select four operation modes with different levels of spatial redundancy and area efficiency. We evaluate the aging effect due to negative bias temperature instability and illustrate that periodically alternating active cells with resting ones will greatly mitigate the effects of the aging process with a negligible power overhead. The area of circuits that are added for immunity to soft errors and for mitigating aging effects is 29.3% of the proposed reconfigurable device. A fault-tolerance evaluation of a Viterbi decoder mapped on the architecture suggests that there is a considerable tradeoff between reliability and area overhead. Finally, we design and fabricate a test chip that contains a 4 × 8 cluster array in a 65-nm process and demonstrate its immunity to soft errors. Accelerated tests using an alpha particle foil showed that the mean time to failure and failure in time are well characterized with the number of sensitive bits and that our architecture can trade off soft error immunity with the area of implementation.

A scheme for avoiding delay faults with slack assessment during standby time is proposed in this paper. The proposed scheme performs path delay testing and checks if the slack is larger than a threshold value using selectable delay embedded in basic elements (BE) on a coarse-grained reconfigurable device. If the slack is smaller than the threshold, a pair of BEs to be replaced, which maximizes the path slack, is identified. Experimental results show that for aging-induced delay degradation a small threshold slack, which is less than 1 ps in a test case, is enough to ensure the delay fault prediction.

We present an adaptive technique for compensating manufacturing and environmental variability in subthreshold circuits using “canary flip-flop (FF),” which can predict timing errors. A 32-bit Kogge-Stone adder whose performance was controlled by body-biasing was fabricated in a 65-nm CMOS process. Measurement results show that the adaptive control can compensate process, supply voltage, and temperature variations and improve the energy efficiency of subthreshold circuits by up to 46% compared to worst-case design and operation with guardbanding. We also discuss how to determine design parameters, such as the inserted location and the buffer delay of the canary FF, supposing two approaches: configuration in the design phase and post-silicon tuning.

Fault avoidance methods on dynamically reconfigurable devices have been proposed to extend device life-time, while their quantitative comparison has not been sufficiently presented. This paper shows results of quantitative life-time evaluation by simulating fault avoidance procedures of representative five methods under the same conditions of wear-out scenario, application and device architecture. Experimental results reveal 1) MTTF is highly correlated with the number of avoided faults, 2) there is the efficiency difference of spare usage in five fault avoidance methods, and 3) spares should be prevented from wear-out not to spoil life-time enhancement.

This paper presents an adaptive technique for compensating manufacturing and environmental variability in subthreshold circuits using ¿canary flip-flop¿ that can predict timing errors. A 32-bit Kogge-Stone adder whose performance was controlled by body-biasing was fabricated in a 65 nm CMOS process. Measurement results show that the adaptive control can reduce the power dissipation by 46% in comparison with the worst-case design with guardbanding.

This paper presents transistor variability modeling and its validation for body-biased subthreshold circuits based on measurements of a device-array circuit using a 90-nm technology. The device array consists of p/nMOS transistors and ring oscillators. We examine and confirm the correlation between the performance variation model extracted from measured I-V characteristics and fabricated oscillation frequencies. We demonstrate that delay variations in subthreshold circuits are well characterized with two parameters, i.e., threshold voltage and subthreshold swing parameter. We also reveal that threshold voltage shift by body biasing can be deterministically modeled and statistical modeling is less meaningful.

Timing margin of a chip varies chip by chip due to manufacturing variability, and depends on operating environment and aging. Adaptive speed control with timing error prediction is a promising approach to mitigate the timing margin variation, whereas it inherently has a critical risk of timing error occurrence when a circuit is slowed down. This paper presents how to evaluate the relation between timing error rate and power dissipation in self-adaptive circuits with timing error prediction. The discussion is experimentally validated using a 32-bit ripple carry adder in subthreshold operation in a 90nm CMOS process. We show a trade-off between timing error rate and power dissipation, and reveal the dependency of the trade-off on design parameters.

This paper proposes a coarse-grained dynamically reconfigurable architecture, which offers flexible reliability to soft errors and aging. A notion of cluster is introduced as a basic element of the proposed architecture, each of which can select four operation modes with different levels of spatial redundancy and area-efficiency. Evaluation of permanent error rates demonstrates that four different reliability levels can be achieved by the proposed architecture. We also evaluate aging effect due to NBTI, and illustrate that alternating active cells with resting ones periodically will greatly mitigate the aging process with negligible power overhead. The area of additional circuits to attain immunity to soft errors and reliability configuration is 26.6% of the proposed reconfigurable device. Finally, a fault-tolerance evaluation of Viterbi decoder mapped on the proposed architecture suggests that there is a considerable trade-off between reliability and area overhead.

Post-fabrication tuning for mitigating manufacturing variability is receiving a significant attention. To reduce leakage increase involved in performance compensation by body biasing, body bias clustering methods have been proposed. However, conventional methods suffer from a large test cost for tuning after fabrication, since there are a tremendous number of body bias assignments. We in this paper propose a low-cost tuning scheme after fabrication and present a layout aware body bias clustering method. The proposed method estimates average leakage power after post-fabrication tuning, and minimizes it. We applied the proposed method to ultralow voltage circuits for suppressing their high sensitivity to random Vth variability, and demonstrated the effectiveness of the proposed method. In the experiments, by just introducing two clusters, leakage power after post-fabrication tuning was reduced by up to 70% compared to a single cluster case.

Body-biasing is expected to be a common design technique, then area efficient implementation in layout has been demanded. Body-biasing outside standard cells is one of possible layouts. However in this case body-bias controllability, especially when forward bias is applied, is a concern. To investigate the controllability, we fabricated a ring oscillator in a 90nm technology, and measured the controllability. Our measurement result and evaluation of area efficiency reveal that body-biased circuits can be implemented with area overhead of less than 1% yet with sufficient speed controllability.

This paper presents modeling of manufacturing variability and body bias effect for subthreshold circuits based on measurement of a device array circuit in a 90nm technology. The device array consists of P/NMOS transistors and ring oscillators. This work verifies the correlation between the variation model extracted from IV measurement results and oscillation frequencies, which means the transistor-level variation model is examined and confirmed in terms of circuit performance. We demonstrate that delay variations of subthreshold circuits are well characterized with two parameters - threshold voltage and subthreshold swing parameter. We reveal that body bias effect is a less statistical phenomenon and threshold voltage shift by body biasing can be modeled deterministically.

A cipher core has been implemented, which is dedicated to a 64-bit block, 128-bit key, dynamically reconfigurable hardware-based cipher, called "Chameleon", in which two 32-cell, 8-context dynamically reconfigurable hardware units are employed to generate new subkeys for each of the 16 iterations in the encryption/decryption process. The proposed architecture has been implemented by 0.6 um CMOS3LM technology, using 65.6K transistors and attaining a maximum throughput of 317.5 Mbps. The new approach demonstrates distinctive features of enhanced complexity and flexibility dedicatedly for embedded encryption/decryption applications in the mobile computing.