The N -body problem is a classical computational challenge that involves integrating the motion equations of a system of interacting bodies. This problem is computationally demanding and, as power consumption becomes a critical issue in computing systems, increasing the energy efficiency of solutions is essential. To address this, we use FPGA accelerators to implement the acceleration computation, the most demanding part of the integration algorithm. FPGAs are known for their low power requirements and high internal parallelism, but they traditionally require hardware programming skills. With High-Level Synthesis (HLS) now well established, we leverage the AMD Vitis HLS toolchain to implement the acceleration computation for the N-body problem. After analyzing the various forms of parallelism at different levels of granularity in the acceleration computation, we design a parallel architecture, implemented on an FPGA using the HLS flow. The speed and energy efficiency of our solution are compared against high-end CPU implementations, showing substantial improvements. Our FPGA implementation achieves 30.4 GPair/s and $697\ \mathrm{MPair} / \mathrm{s} / \mathrm{W}$, significantly outperforming previous FPGA and CPU solutions in both speed and power consumption.

The TEXTAROSSA project aims to bridge the technology gaps that exascale computing systems will face in the near future in order to overcome their performance and energy efficiency challenges. This project provides solutions for improved energy efficiency and thermal control, seamless integration of heterogeneous accelerators in HPC multi-node platforms, and new arithmetic methods. Challenges are tacked through a co-design approach to heterogeneous HPC solutions, supported by the integration and extension of HW and SW IPs, programming models, and tools derived from European research.

Writing good code for FPGA is a challenge “per se”, but also running already existing and optimized FPGA kernels often requires writing specific “host side” code and some target hardware knowledge to achieve good performances. In this work, we describe a FastFlow extension supporting seamless off loading of tasks to FPGA, once an FPGA kernel is available. In particular, we show how kernels implemented in Vitis and running on XILINX Alveo FPGA boards may be integrated to implement “normal” parallel stages (pipeline stages, map/farm workers) in a structured parallel FastFlow computation. Experimental results are shown, demonstrating the feasibility of the approach.

To achieve high performance and high energy efficiency on near-future exascale computing systems, three key technology gaps needs to be bridged. These gaps include: energy efficiency and thermal control; extreme computation efficiency via HW acceleration and new arithmetics; methods and tools for seamless integration of reconfigurable accelerators in heterogeneous HPC multi-node platforms. TEXTAROSSA aims at tackling this gap through a co-design approach to heterogeneous HPC solutions, supported by the integration and extension of HW and SW IPs, programming models and tools derived from European research.

Summary form only given. We address the design of pipelined systems able to sustain the throughput of a given periodic task and, at the same time, to serve aperiodic requests associated with hard real-time constraints. The proposed method is based on the allocation of the global graph (periodic and aperiodic tasks), over-dimensioning the design of the system devoted to process the periodic task, deserving the unused parts of the resources to the management of aperiodic requests. A formal definition of such a mapping problem, together with the formalization of the searching space, is given. The searching space is structured in a way such as the minimization process moves toward a solution, which satisfies, if possible, all the real-time constraints and has minimal HW requirements. Once formulated as a minimization problem, the pipelined architecture and the corresponding scheduling are determined by means of a simulated annealing algorithm. A theorem is given to ensure that all the feasible mappings are reachable in the optimization process.

Abstract This work presents the architecture of PROSIDIS, a special purpose processor designed to search for the occurrence of substrings similar to a given ‘template string’ within a proteome. Similarity is determined by means of a weighting matrix which measures the degree of similarity between any two amino acids. The paper recalls the basis of the PHG (Parallel Hardware Generator) tool, developed in the framework of the HADES project (Hardware Design for Scientific Applications). Through PHG it is possible to design, in a nearly automatic way, a parallel hardware which efficiently implements an algorithm described through recurrence equations; PHG is able to generate a synthesizable VHDL which represents a parallel system derived from the System of Affine Recurrence Equations (SARE) describing the problem. In this work we illustrate the advantages derived from designing a special purpose processor to face the protein similarity discovery problem. Some preliminary results are given, reporting the time spent by several conventional computing architectures and by the PROSIDIS processor hosted by a personal computer to solve the same protein analysis problem. The results show that PROSIDIS, implemented on a Xilinx XV1000 FPGA, gives speedup figures ranging from 5.6 up to 55.6. Copyright © 2004 John Wiley & Sons, Ltd.

UNLABELLED: We present the architecture of PROSIDIS, a special purpose co-processor designed to search for the occurrence of substrings similar to a given 'template string' within a proteome. Actual tests show speed up figures ranging from 5 to 50 with respect to conventional general-purpose processors. AVAILABILITY: the PROSIDIS configuration file and the c code are available at http://www.enea.it/hpcn/php/rosato/

The rigorous characterization of the behaviour of a radiobase antenna for wireless communication systems is a hot topic both for antenna or communication system design and for radioprotection-hazard reasons. Such a characterization deserves a numerical solution, and the use of a Finite-Difference Time-Domain (FD-TD) approach is one of the most attractive candidates. Unfortunately it has strong memory and CPU-time requirements. Numerical complexity can be successfully afforded by using parallel computing. In this work we discuss the parallel implementation of the FD-TD code, individuating the theoretical lower bound for its parallel execution time, and we present the findings achieved on the APE/Quadrics SIMD massively parallel systems. Results, obtained from the simulation of actual radiobase antennas, clearly demonstrate that massively parallel processing is a viable approach to solve EM problems, allowing the simulation of radiating devices, which could not be modeled through conventional computing systems. The tests on actual systems evidenced sustained computational speed equal to 17% of the theoretical maximum.

We describe a design methodology which allows a fast design and prototyping of dedicated hardware devices to be used in heterogeneous computations. The platforms used in heterogeneous computations consist of a general-purpose COTS architecture which hosts a dedicated hardware device; parts of the computation are mapped onto the former, parts onto the latter, in a way to improve the overall computation efficiency. We report the design and the prototyping of a FPGA-based hardware board to be used in the search of low-autocorrelation binary sequences. The circuit has been designed by using a recently developed Parallel Hardware Generator (PHG) package which produces a synthesizable VHDL code starting from the specific algorithm expressed as a System of Affine Recurrence Equations (SARE). The performance of the realized devices has been compared to those obtained on the same numerical application on several computational platforms.

In this paper we present the toroidal neural networks (TNN), a new class of neural network derived from discrete time-cellular neural networks (DT-CNN). TNN are characterized by 2D toroidal topology with local connections, by binary outputs and by a simple equation describing the dynamic of neuron states; binary outputs are obtained comparing initial and final states. Due to the expression of state dynamic, TNN learning has a very appealing geometric interpretation: a transformation, specified by means of a training input sequence, is represented through a polyhedron in the TNN weight space. Along with the definition and theory of TNN, we present a learning algorithm which, for a given transformation expressed by means of a training sequence, gives the set of TNN weights (if existing) which exactly implement the transformation: such a set of weights is a point belonging to the polyhedron representing the training sequence. Furthermore, the algorithm gives the exact minimal spatial locality characterizing the problem; in order to reduce the number of TNN weights, a heuristic is used to try to move neuron connectivity from the spatial to the temporal dimension.

The automatic extraction of parallelism from algorithms, and the consequent parallel code generation, is a challenging problem. We present a procedure for automatic parallel code generation in the case of algorithms described through a SARE (Set of Affine Recurrence Equations). Starting from the original SARE description in an N-dimensional iteration space, the algorithm is converted into a parallel code for an (eventually virtual) m-dimensional distributed memory parallel machine (m

The authors propose a method to implement Acyclic Data Flow Graphs (ADFG) in any general purpose multiprocessor system supporting a CSP type language. The granularity of ADFG nodes is discussed During ADFG analysis the authors use fine granularity to exploit all the parallelism inherent in the problem. When the graph G has been allocated, it is divided into P subgraphs G/sub k/ (P is the number of the processors in the network); each of them is assigned to a processor P/sub k/. G/sub k/ still presents some parallelism which cannot be usefully exploited and which implies a certain amount of overhead during G/sub k/ execution; the authors reduce this overhead by executing a post allocation analysis which increases the granularity of G/sub k/ nodes. In order to evaluate GTP performances the Overhead Reduction Ratio (ORR) is introduced. ORR is computed by using the results of several executions of GTP on randomly generated ADFG; the presented tests show the effectiveness of GTP.>