A high performance parallel network simulation environment was developed in the SR2201 project, The SR2201 is one of the highest performance massively parallel supercomputers in the world. The enhanced simulation algorithm achieved a 2.4 times increase in simulation speed compared with conventional simulation methodology. A 98% detection rate for all design errors before physical design contributed to the shortening of development time.

A new fault simulator (VFSIM) for synchronous sequential circuits has been developed and applied to random access scan circuits of several hundred LSIs in mainframe computers.The results show that VFSIM is one or two orders of magnitude faster than a conventional fault simulator designed for random access scan circuits.A vectorized pattern parallel event-driven method is introduced for accelerating the fault simulator for synchronous sequential circuits.Utilizing the concept of unobservable regions (UOR), in which simulation of temporarily unobservable faults is avoided, contributes greatly to further acceleration, especially for random access scan circuits.

This paper describes the algorithm, implementation, and evaluation results of a new fault simulator called RFSIM, which is designed for combinational circuits. In order to accelerate fault simulation, two basic principles are introduced, a Detectable Fault Only (DFO) principle and a Candidate Gate Once (CGO) principle. The DFO principle is a dynamic reduction algorithm, which aims at drastically reducing computational complexity by utilizing blocking gate information. The CGO principle is an implementation technique which is utilized to implement the DFO principle effectively. Experimental results show that RFSIM is more than 10 times faster than a conventional concurrent fault simulator, and confirms that the DFO principle contributes to a drastic reduction in the number of faults to be simulated. A fault reduction ratio of around 25 to 1 was achieved in one of the benchmark circuits.