By utilizing the mapping-based pulse width modulation (MPWM), the look-up-table (LUT) based all digital transmitter (ADT) features a superb in-band signal-to-noise ratio (SNR), but its rather high random-access memory (RAM) consumption and the computation complexity hinder its further usage in applications requiring real-time reconfigurability. Our previous work leverages a Viterbi-based PWM (VbPWM) scheme to provide an iterative deduction approach, but the degraded performance and the excessive register usage make it unsuitable for real applications. By exploring the quais-periodicity inside the differenced target function, a Viterbi-based multi-bit deduction PWM (VMbPWM) is proposed in this paper, which leverages the periodic-like feature of the target function to form a multiple-bit deduction process of the 1-bit pulse sequence. Numerical simulations suggest that the proposed scheme outperforms the MPWM by a maximum of 19 dB in in-band SNR when deducing 8 bits in a single iteration, and a maximum of 10 dB increase in SNR is presented for the VMbPWM over VbPWM when the two possess the same computation complexity. After combining iterations that deduce different amounts of bits, the computation complexity of VMbPWM can be reduced to nearly 1/4 of that when deducing 8 bits in each iteration at the cost of a 5 dB SNR degradation. Accordingly, a fully pipelined ADT structure is conducted based on the VMbPWM and is implemented with the ZCU102 evaluation kit. As depicted by the implementation results, the proposed VMbPWM-based ADT reduces the RAM usage to two tiles while eliminating the register usage from 22% using VbPWM to 15% using VMbPWM. Moreover, a reduced error vector magnitude (EVM) is demonstrated for the VMbPWM, where the maximum EVM turns out to be 2.6%, 4.0%, and 4.9% under the symbol rate of 5 MBaud, 25 MBaud, and 50 MBaud using 64QAM, which is typically 0.1%-0.2% lower than the VbPWM.

Based on the concept of mapping-based pulse width modulation (MPWM), the look-up-table-based all-digital transmitter (LUT-based ADT) achieves high signal-to-noise ratio (SNR) and low error vector magnitude (EVM) by leveraging a stored mapping from the baseband complex sample to the output binary sequence, while its high RAM consumption and LUT generation complexity hinder its further usage. Toward a RAM-free and traversal-free ADT based on MPWM, in this paper, we model the MPWM process as an optimization problem and correspondingly construct a Viterbi-based PWM (VbPWM) modulator scheme, featuring real-time deduction of the 1-bit sequence from the input complex sample and a traversal-free computation process. Fixed points simulations suggest that the deduced local optimum demonstrates a 10 dB SNR loss compared with the global optimum of MPWM, while this loss can be further eased by 2-3 dB after introducing a simplified simulated annealing algorithm. Additionally, a fully serial and pipelined implementation structure is proposed to unfold the iterations into cascading iteration units, thereby achieving run-time reconfigurable carrier frequencies and minimizing block read-only memory (BRAM) usage. EVMs of the proposed ADT with carrier frequencies ranging from 0.6 GHz and 7.6 GHz under different symbol rates are measured with ZCU102, presenting an increasing trend associated with carrier frequency and symbol rates. Consequently, compared with the original MPWM, a 1% loss of EVM is revealed under 5 MBaud of symbol rate for all measured frequencies. The maximum EVM under 5 MBaud is measured as 3.5%, while the maximum for 25 MBaud and 50 MBaud is 5% and 5.8%, respectively. The RAM usage is then minimized to a single 36K tile and the traversal of MPWM is removed.

The bandwidth of the frequency-modulated continuous wave (FMCW) system is largely increased with the progress in high-speed technology to achieve high accuracy ranging. In situations where bandwidth is restricted, the range estimation algorithm is still worth concern. By breaking down the range estimation of the FMCW system into single-tone frequency estimation, in this paper we propose a Phase-Difference-based Single-Tone estimation (PDb-STE) algorithm consisting of two fast Fourier transform (FFT) units and an interpolator. Spectra obtained from the FFT units are utilized to form a phase difference, which is used for the FFT enhancement. Frequency, phase and amplitude estimations are carried out based on the corrected phase difference. Theoretical proof of the proposed algorithm is given under the rectangular window and further applied with Hann, Hanning, Blackman and Kaiser windows during simulation. The results show that for Kaiser window the expanded main lobe brings less systematic error for both complex signal estimation and in-phase part estimation. Simulation of FMCW system is performed based on proposed algorithm. By setting iteration chirp-Z transform (CZT) as the comparison, the proposed algorithm outperforms the CZT by 1 dB under rectangular and Kaiser window with the main lobe control factor β ≤ 2.5. The performance worsens as the β grows, which is due to the increased noise disruption to the wide main lobe. Hardware verification is carried out to show the feasibility of the algorithm and obtain results with all root mean square error(RMSE) below 0.02 m.

Long period digital random sequence plays an important role in reliable communications and high security scenarios. This paper improved the method of generating long period digital random sequences based on the Residue Number System (RNS) and the Chinese Remainder Theorem (CRT), and a sequence mapping method after CRT extension. This paper proves that the period of sequence after mapping will not degenerate if the modulus used in the mapping stage is coprime with the period of the original sequence. By using the parallelism of RNS, the proposed method can generate sequences at high speed with fewer hardware resources. The NIST test results show that the pass rate of each test item is above 98.40%, which meets the NIST test confidence requirements, confirming the randomness of the generated sequences. An image encryption test is given as one of the example applications of the generated sequences. On the theoretical basis, by jointly optimizing the sequence mapping and iteration procedure, a hardware implementation architecture is also presented in this paper. The implementation is based on Xilinx XC7Z020CLG484-3 FPGA and compared with the implementations of classical chaotic maps. The results show that the proposed architecture has longer sequence period with less hardware resource consumption and higher generation speed and is more general. Meanwhile, the proposed architecture has fast phase switching ability, which is about 10 clock periods. This is one of the key attributes when the sequence is used in communication systems.

Runtime log-based anomaly detection is one of several key building blocks in ensuring system security, as well as post-incident forensic investigations. However, existing log-based anomaly detection approaches that are implemented on large-scale Internet of Things (IoT) systems generally upload local data from edge devices to a centralized (cloud) server for processing and analysis. Such a workflow incurs significant communication and computation overheads, with potential privacy implications. Hence, in this paper, we propose a customizable and communication-efficient federated anomaly detection scheme (hereafter referred to as FedLog), designed to facilitate the identification of abnormal log patterns in large-scale IoT systems. Specifically, we first craft a Temporal Convolutional Network-Attention Mechanism-based Convolutional Neural Network (TCN-ACNN) model, to effectively extract fine-grained features from system logs. Second, we develop a new federated learning framework to support IoT devices in establishing a comprehensive anomaly detection model in a collaborative and privacy-preserving manner. Third, a lottery ticket hypothesis based masking strategy is designed to achieve customizable and communication-efficient federated learning in handling non-Independent and Identically Distributed (non-IID) log datasets. We then evaluate the performance of our proposed scheme with those of DeepLog (published in CCS, 2017) and Loganomaly (published in IJCAI, 2019) in both centralized learning and federated learning settings, using two publicly available and widely used real-world datasets (i.e., HDFS and BGL). The findings demonstrate the utility of the proposed FedLog scheme, in terms of log-based anomaly detection.

The increasing demand for privacy protection facilitates growing interests in Federated Learning (FL). Nevertheless, most of existing FL schemes are susceptible to malicious participating clients compromised by Byzantine attacks, which remains a challenging issue. In this paper, we propose a novel Byzantine-robust FL scheme, coined FLPhish. Specifically, we first design a ensemble learning-based FL architecture, named Ensemble Federated Learning (Ensemble FL). Second, a phishing mechanism is crafted for the FL architecture to detect abnormal client behaviors. Third, a reputation mechanism is developed to further identify malicious participating clients compromised by Byzantine attackers. We evaluate the performance of FLPhish by considering various fractions of Byzantine clients and various imbalance degrees of the data distribution. Extensive experiments demonstrate the high effectiveness of the proposed FLPhish scheme in resisting Byzantine attacks in Ensemble FL.

In this paper, we proposed a FPGA implementation architecture for SVM classifier. The architecture is based on the proposed Shared Dot Product Matrix (SDPM) method which computes and stores the dot product of all training data before SVM searching process. We implemented the proposed method by software simulation and hardware implementation. The software simulation of SDPM method achieves twice the speed of LIBSVM, which is one of the most popular SVM implementation libraries. This acceleration mainly results from the reduction of repeat Kernel function calculation. Then the hardware software collaboration architecture for SDPM is also proposed in this paper. Results show that the proposed architecture achieves approximately 30 times faster searching speed compared with LIBSVM.

Advances in small and low power electronics have created new opportunities for the Internet of Things (IoT), leading to an explosion of physical objects being connected to the Internet. However, there still lacks an indoor localization solution that can answer the needs of various location-based IoT applications with desired simplicity, robustness, accuracy, and responsiveness. We introduce Foglight, a visible light enabled indoor localization system for IoT devices that relies on unique spatial encoding produced when mechanical mirrors inside a projector are flipped based on gray-coded binary images. Foglight employs simple off-the-shelf light sensors that can be easily coupled with existing IoT devices-such as thermometers, gas meters, or light switches-making their location discoverable. Our sensor unit is computation efficient; it can perform highaccuracy localization with minimum signal processing overhead, allowing any low-power IoT device on which it rests to be able to locate itself. Additionally, results from our evaluation reveal that Foglight can locate a target device with an average accuracy of 1.7 mm and average refresh rate of 84 Hz with minimal latency, 31.46 ms on Wi-Fi and 23.2 ms on serial communication. Two example applications are developed to demonstrate possible scenarios as proof of concept. We also discuss limitations, how they could be overcome, and propose next steps.

We present Lift, a visible light-enabled finger tracking and object localization technique that allows users to perform freestyle multi-touch gestures on any object's surface in an everyday environment. By projecting encoded visible patterns onto an object's surface (e.g. paper, display, or table), and localizing the user's fingers with light sensors, Lift offers users a richer interactive space than the device's existing interfaces. Additionally, everyday objects can be augmented by attaching sensor units onto their surface to accept multi-touch gesture input. We also present two applications as proof of concept. Finally, results from our experiments indicate that Lift can localize ten fingers simultaneously with an average accuracy of 1.7 millimeter and an average refresh rate of 84 Hz with 31 milliseconds delay on WiFi and 23 milliseconds delay on serial communication, making gesture recognition on non-instrumented objects possible.

In this paper, we present the design and implementation of toy car localization and navigation system, which enables toy cars and "passengers" to learn and exchange their fine-grained locations in an indoor environment with the help of the projected light based localization technique. The projected light consists of a sequence of gray code images which assigns each pixel in the projection area a unique gray code to distinguish their coordination. The light sensors installed on a toy cars and a potential "passenger" receive the light streams from the projected light, based on which their locations are inferred. The toy car then utilizes A* algorithm to plan a route based on its location, its orientation, the target's location and the map of "roads". The fast speed of projected light based localization technique enables the toy car to adjust its own orientation while "driving" and keep itself on "roads". The toy car system demonstrates that the localization technique and the client-server architecture can benefit similar applications that require fine-grained location information of multiple objects simultaneously.

We present the "Honeycomb", a microcontroller platform that can easily be networked into hexagonal lattices of hundreds of nodes to create novel materials that tightly integrate sensing, actuation, computation and communication. The tool-chain consists of the platforms, a viral boot-loader to virally disseminate programs into the network, a software library that facilitates sensing, control, and communication, and software tools that allow interacting with the network from a host computer. After a brief tutorial, participants will have an opportunity to experiment with the Honeycomb hardware, which will be made available during the studio, write code for distributed processing of sensor information, and drive various actuators ranging from multi-color lights to servo motors, with the goal to construct an interactive installation to be displayed at the conference. All materials, including open source hardware and software will be made available on the web prior to the studio.