Security for Cyber physical systems includes not only guaranteeing operational security of data they process, but preventing malicious alteration of their execution due to knowledge of their underlying structure. With the advent of software in the form of reprogrammable hardware descriptions, protection of field programmable units from malicious reverse engineering and subversion becomes more critical. We compare four different white-box transformation algorithms aimed at hindering adversarial reverse engineering by changing component and signal configurations within combinational logic programs. We present security and efficiency analysis for these techniques and show positive results for achieving measurable hiding of signal and component information.

Radio-frequency distinct native attribute (RF-DNA) fingerprinting is adapted as a physical-layer technique to improve the security of integrated circuit (IC)-based multifactor authentication systems. Device recognition tasks (both identification and verification) are accomplished by passively monitoring and exploiting the intrinsic features of an IC's unintentional RF emissions without requiring any modification to the device being analyzed. Device discrimination is achieved using RF-DNA fingerprints comprised of higher order statistical features based on instantaneous amplitude, phase, and frequency responses as a device executes a sequence of operations. The recognition system is trained using multiple discriminant analysis to reduce data dimensionality while retaining class separability, and the resultant fingerprints are classified using a linear Bayesian classifier. Demonstrated identification and verification performance includes average identification accuracy of greater than 99.5% and equal error rates of less than 0.05% for 40 near-identical devices. Depending on the level of required classification accuracy, RF-DNA fingerprint-based authentication is well-suited for implementation as a countermeasure to device cloning, and is promising for use in a wide variety of related security problems.

Field programmable gate arrays (FPGAs) have become increasingly popular in circuit development due to their rapid development times and low costs. With their increased use, the need to protect their intellectual property (IP) becomes more urgent. The digital fingerprint accomplishes this by creating a unique identification (ID) for each FPGA. In this research, we propose methods to dramatically increase the stability and robustness of the digital fingerprint ID by the proper choice of input sequences. We also show that by properly choosing the input word, we can significantly increase the DF resistance to operating temperature changes.

The susceptibility of digital systems to tampering is of immense concern to military and commercial organizations. Current defenses against such techniques as reverse engineering and side channel analysis are limited and don't address the underlying vulnerable characteristics of digital circuits. In this paper, we propose a generalized defense methodology named dynamic polymorphic reconfiguration that significantly reduces the probability of successful tampering. We achieve protection through targeted component hiding and the introduction of run-time autonomous defense adaptations. As a result, we establish the feasibility of self-protecting circuits.

Creating digital circuits of ever decreasing size leads to certain imperfections that cannot be avoided. Although these imperfections are not significant enough to hinder the digital circuit operation, they are random and can be exploited to create a unique digital fingerprint which can be used as a chip identity. Unique digital fingerprints can be created on any number of circuits and in our research we created 60 digital fingerprints, all of which were uniquely identifiable. The digital fingerprint is a function of the amount of combinational logic that forms the circuit and can be applied to any sufficiently large combinational circuit. In this research, we have used a combinational multiplier and we show how a longer combinational path leads to a larger number of captured glitches. In addition, we show the effects of temperature changes on the digital fingerprint.

In this paper, we proposes the concept of creating a circuit identifier, or digital fingerprint, for field programmable gate arrays (FPGAs). The digital fingerprint is a function of the natural variations in the semiconductor manufacturing process that cannot be duplicated or forged. The proposed digital fingerprint allows the use of any arbitrary of nodes internal to the circuit or the circuit outputs as monitoring locations. Changes in the signal on a selected node or output can be quantified digitally over a period of time or at a specific instance of time. Two monitoring methods are proposed, one using cumulative observation of the nodes and the other samples the nodes based on a signal transition. Two monitoring methods were validated on a small sample of twenty XilinxregVirtex-II Pro FPGAs, where both methods successfully created unique identifiers for each FPGA.

In this paper, we discuss the method of creating a circuit identifier, or digital fingerprint, for field programmable gate arrays (FPGAs). The proposed digital fingerprint is a function of the natural variations in the semiconductor manufacturing process that cannot be duplicated or forged. The proposed digital fingerprint allows the use of any arbitrary of nodes internal to the circuit or the circuit outputs as monitoring locations. Changes in the signal on a selected node or output can be quantified digitally over a period of time or at a specific instance of time. Two monitoring methods are proposed, one using cumulative observation of the nodes and the other samples the nodes based on a signal transition. Two monitoring methods were validated on a small sample of twenty XilinxregVirtex-II Pro FPGAs, where both methods successfully created unique identifiers for each FPGA. In addition, the effects of temperature and voltage fluctuations are also discussed.

As field programmable gate arrays (FPGAs) become more widely used, security concerns have been raised regarding FPGA use for cryptographic, sensitive, or proprietary data. Storing or implementing proprietary code and designs on FPGAs could result in the compromise of sensitive information if the FPGA device was physically relinquished or remotely accessible to adversaries seeking to obtain the information. A hardware description language (HDL) FPGA architecture supporting dynamic reconfiguration through granular reconfiguration control is presented for use in security applications. Testing validates the reconfiguration results and compares power usage, timing, and area estimates from a conventional and Dynamically Reconfigurable FPGA (DRFPGA) model.

Current FPGA architectures are limited in the area of granular reconfiguration. This is largely due to the limited use of reconfigurable designs and the focus on reconfiguring entire modules as opposed to fine details of a design. The ability to reconfigure a circuits' characteristics can have huge rewards in the areas of circuit survivability, fault tolerance and anti tamper. This paper addresses this need as well as a proposed dynamically reconfigurable FPGA implementing custom retiming algorithms combined with dynamic signature generation. Through the use of this design, users can significantly increase their level of control of an FPGA design in an effort to address the problems of anti-tamper, circuit survivability and fault tolerance.

In the drive to create ever smaller transistors, conventional silicon CMOS devices are becoming more difficult to fabricate reliably as process size shrinks. New technologies are being investigated to replace silicon CMOS. While offering greater numbers of devices per unit area, all of these technologies are more difficult to fabricate, and more likely to fail in operation than current technologies. Nanotechnology research has identified the need for fault and defect tolerance at the architectural level so that future devices can be used in large-scale electronics circuits. This paper examines the problem of creating reliable caches using extremely unreliable technologies. We incorporate support logic (i.e., control, datapath, and self-test logic) into the analysis, and propose a novel Content Addressable Memory-based design incorporating "best practice" fault tolerant design techniques. The design requires 15 times the number of devices of a conventional design, but enables the use of device technologies with defect rates higher than 10-6, a three order of magnitude improvement over non-fault tolerant designs

Field-programmable gate arrays (FPGAs) are increasingly used in system designs, but their vulnerability to reverse engineering could lead to lost profits or security breaches. Thus, high FPGA design security is needed with low performance penalties and low realization and maintenance costs. Using a novel circuit modification method, common circuits were augmented with decoy circuits for protection. Security values for the original and modified circuits were calculated, and the original and modified circuits' execution times, power consumptions, and resource usages were collected from simulations. For the modified circuits, security improved by six orders of magnitude, yet execution times, power consumption, and resource usage increased by less than one order of magnitude. The proposed algorithm has demonstrated the potential for substantial increases in FPGA design security at a low cost, and could also be applied to application-specific integrated circuits (ASICs)

The issues of using errorful data in motion estimation and of using feedback to improve feature extraction and matching in incremental analysis are addressed. Initial noisy correspondence data are continously refined by removing those parts that do not fit the estimated 3-D motion parameters. The extraction of a tracked region is guided by its expected properties obtained from the corresponding objects in the previous frames. The surfaces of objects are reconstructed from a sparse depth map.>

In automated feature-based motion analysis of multiple frames, correspondence data are usually noisy and fragmented. A technique that gradually refines the initial noisy correspondence data and links fragments of a single trajectory using feedback from 3D motion estimation is presented. First, 3D motion parameters are estimated using the initial correspondence data. Then, each noisy trajectory is partitioned into subsets of points, each of which conforms to the estimated motion. The best set is used as the input to the next motion estimation. This process is repeated, and the gaps in the refined correspondence data are filled by guidance from the predicted motion. Test results for a standard real image sequence are presented.>