Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page
Demo Data from EDBT 2026 / reviewers in the wild / expert

Suranjan Ghose

dblp:50/2798 · DBLP profile ↗
← Back
3ranked-venue papers
0as first author
0since 2021 · last 2008
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2Theory of computation · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 87% Hardware accelerators and domain-specific architectures · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing › parallel algorithms › graph algorithms
all-pairs shortest paths		 0.011986
A Parallel Algorithm to Compute the Shortest Paths and Diameter of a Graph and Its VLSI Implementation · IEEE Trans. Computers 1986
Parallel and multicore computing
parallel graph algorithms		 0.011986
A Parallel Algorithm to Compute the Shortest Paths and Diameter of a Graph and Its VLSI Implementation · IEEE Trans. Computers 1986
Hardware accelerators and domain-specific architectures
systolic array		 0.011986
A Parallel Algorithm to Compute the Shortest Paths and Diameter of a Graph and Its VLSI Implementation · IEEE Trans. Computers 1986

Methods — techniques the papers use, named apart from their topics

systolic array · 0.0
YearPublicationVenuePosition
2008 Fast deterministic broadcast and gossiping algorithms for mobile ad hoc networks
Koushik Sinha, Suranjan Ghose, Pradip K. Srimani
 J. Parallel Distributed Comput.2
1986 A Parallel Algorithm to Compute the Shortest Paths and Diameter of a Graph and Its VLSI Implementation
abstract
In this correspondence we develop a parallel algorithm to compute the all-pairs shortest paths and the diameter of a given graph. Next, this algorithm is mapped into a suitable VLSI systolic architecture and the performance of this proposed VLSI implementation is evaluated.
Bhabani P. Sinha, Bhargab B. Bhattacharya, Suranjan Ghose, Pradip K. Srimani
 IEEE Trans. Computers3
1984 Heuristic Search Approach to Optimal Routing in a Distributed Architecture
Bhargab B. Bhattacharya, Suranjan Ghose, Bhabani P. Sinha, Pradip K. Srimani
 FSTTCS2