Current processor chip designs are mainly oriented by performance, power and area (PPA), and developed using the waterfall model. However, there are two main challenges in this development model: 1) The end-to-end iteration cycle and cost of processor chip development are too high, and cannot flexibly respond to changes in chip fragmented design specifications. 2) Processor chip verification is less agile, and there is a lack of a full-chain processor agile design platform that can be easily ported to different development environments. To tackle both issues, we propose an object-oriented hardware agile design methodology, oriented by time, cost, and complexity, and have built the RIVL platform to support the agile development process for processors. RIVL integrates a highly automated design flow for processor RTL design, Integration, Verification, and Layout design to improve processor development efficiency. We achieved tape-out verification of more than 60 RISC-V processors through agile design methods, demonstrating the use and effectiveness of RIVL. We quantify the performance of CoreGen using CoreMark and demonstrate that CoreGen achieves industry-competitive performance.

In digital integrated circuits with multiple power domains, level shifters (LSs) are essential circuit elements that can transform the voltage region from low to high. However, high-frequency gate drivers can generate hundreds of voltages per nanosecond noise (high dV/dt noise). Such high dV/dt noise can cause malfunction of a conventional pulse-triggered cross-coupled LS (CCLS) that is used to control the high-side nMOS switch. In this article, a novel LS with noise immunity is proposed and investigated. Compared with the conventional resistor load LS, the proposed circuit adopts nMOS-R cross-coupled (NRCC) LS, and realizes the selective filtering ability by exploiting the path that filters out the noise introduced by the dV/dt. The high-voltage gate drive integrated circuit (HVIC) is implemented using a 600 V silicon-on-insulator (SOI) BCD process. Analyses and experiments show that the proposed design can help the HVIC maintain a high common-mode transient immunity (CMTI) of up to 137 V/ns while allowing a negative VS swing down to -9.4 V under a 15 V supply voltage. Compared with the traditional HVIC with resistance load LS, the proposed novel HVIC with the NRCC LS improves the noise immunity of dV/dt by 182%.

This article introduces an innovative design of a low-pass (LP) negative group delay (NGD) integrated circuit (IC) in the 180-nm CMOS technology. The LP-NGD circuit is an inductorless topology constituted by RC-network with CMOS metal-insulator-metal (MIM) capacitor and polygate resistor. The design methodology is illustrated by considering the chip layout process. Then, the first run simulation is performed with the design rule check (DRC) and 2.5 mm${\times }$2.2 mm layout versus schematic (LVS) approaches. The feasibility of the CMOS LP-NGD IC circuit implementation is validated with chip-onboard (CoB). The proof of concept (PoC) of the LP-NGD miniaturized circuit was tested in both S-parameter and time domain (TD). As expected, the calculated, simulated, and experimented results of CoB showing NGD of about −10 ns over 12 MHz and −10 dB attenuation are confirmed. The active CMOS LP-NGD technology compensates the insertion loss to 2.4 dB, the GD reaches −11 ns, and the reflection loss reaches −20 dB. Moreover, TD investigations were also performed to show the feasibility of generating pulse and arbitrary waveform signal time advance through the designed and fabricated LP-NGD CoB prototypes.

The temperature range of SPICE models of bipolar and field-effect transistors is extended from the standard commercial level ( -60°C⋯+150°C) to harsh conditions level ( -200°C⋯+300°C) for low/high-temperature ICs design. This is done by including additional equations for temperature-dependent parameters, and by connecting additional elements to the device equivalent circuit to take into account the thermal effects. The universal automated methodology of model parameters extraction from the experimental data measured at low and high temperatures is proposed. The good agreement between simulated and measured device characteristics is achieved. The RMS error is not more than 10%-20%.

A digital current and voltage predictive controller (CVP) is proposed for high switching frequency, low power SMPS. The predictions of the inductor current and capacitor output voltage are performed simultaneously by adopting a flexible PWM pattern that enables dynamic adjustment of the time of the voltage events. The CVP controller preserves the merits of predictive current-mode control and allows to further improve the dynamic performances. With the knowledge of the inductor current, the performances of the CVP controller are analyzed compared to a deadbeat controller. Experimental results of a current sensorless implementation verify better closed-loop performances than those of PID, RST and sliding-mode controllers. The lab-scale prototype implemented in an FPGA supports a switching frequency up to 4 MHz only limited by the discrete buck converter.

This paper presents a novel digital controller for the high-switching-frequency buck converter based on the principle of predictive control. Compared with a traditional current-mode predictive controller, the prediction of the inductor current and the output voltage are performed at the same time by adding a control variable to the DPWM signal that can dynamically adjust the time of voltage jump. It accelerates the convergence rate during transient states, while inherently preserving the rejection of power and reference perturbations. The analysis of controller's operation illustrates the dual-state-variable predictive attributes that lead to the digital implementation. To further enhance the power efficiency of the controller, an 1-1 MASH Σ- Δ DPWM with a feasible dither generation module is proposed to restrain the idle-tone effects without deteriorating the closed-loop stability as well as to preserve reasonable cost in silicon area. Experimental results verify closed-loop operations at switching frequency up to 4 MHz only limited by the discrete buck converter. The converter is well regulated over a large output range with excellent dynamic performances.