Ferroelectric random access memory (FeRAM) is a promising candidate to further dynamic random access memory (DRAM) scaling. However, the design of the FeRAM bit cell is nontrivial as the ferroelectric device model is not well supported by EDA tools. Modern integrated circuit design heavily depends on circuit-level SPICE simulators that integrate compact device models through modified nodal analysis (MNA) representation. This paper presents a novel MNA-based SPICE simulation method for ferroelectric device models, targeted at the design space exploration of FeRAM bitcells. Furthermore, this paper provides a co-design procedure for FeRAM bitcells and sense amplifiers via a comprehensive case study.

An analog memristor crossbar-based Lyapunov equation solver is proposed in this article. It is an extension of memristor crossbar linear equation solver, but taking into account of the regularity with Lyapunov equation in the organization of crossbar. Nonideal effects due to co-design with CMOS analog circuits are studied in detail. Verification using a Verilog-AMS tool is performed to justify that with proper scaling on the memristor conductance values and other circuit signals, the solution quality of Lyapunov matrix equation can be improved.

Since the memristor emerged as a programmable analog storage device, it has stimulated research on the design of analog/mixed-signal circuits with the memristor as the enabler of in-memory computation. Due to the difficulty in evaluating the circuit-level nonidealities of both memristors and CMOS devices, SPICE-accuracy simulation tools are necessary for perfecting the art of neuromorphic analog/mixed-signal circuit design. This article is dedicated to a native SPICE implementation of the memristor device models published in the open literature and develops case studies of applying such a circuit simulation with MOSFET models to study how device-level imperfections can make adversarial effects on the analog circuits that implement neuromorphic analog signal processing. Methods on memristor stamping in the framework of modified nodal analysis formulation are presented, and implementation results are reported. Furthermore, functional simulations on neuromorphic signal processing circuits including memristors and CMOS devices are carried out to validate the effectiveness of the native SPICE implementation of memristor models from the perspectives of simulation accuracy, efficiency, and convergence for large-scale simulation tasks.