This work introduces SENSOTERIC, a multi-partner project that aims at leveraging the properties of emerging Reconfigurable Field Effect Transistors (RFETs) to develop a sensor platform. RFETs will be used for a generic sensor interface and for a dedicated transducer element. In the first case, our goal is to develop an analog front-end interface that can be tuned at runtime to adapt to different environmental conditions and be used in a broad spectrum of applications. This feature shall be enabled by the polarity-control and negative differential resistance characteristics of the reconfigurable devices employed, that are co-integrable on industrial CMOS processes such as 22 nm FDSOI. In the second case, we want to exploit the intrinsic nature of these doping-free devices to yield better 1/f noise performances when compared to classic CMOS transducers. Moreover, the presence of un-gated areas on top of the channel of these devices makes them the perfect candidates to be functionalized. In this early-stage overview of the project, we will introduce the key features and the vision that make SENSOTERIC a unique contribution towards smart sensing solutions in environmental monitoring and healthcare.

The linearity of Sigma Delta Modulators (SDMs) is evaluated performing a Fourier Transform of the output bitstream. The presence of quantization noise complicates this task: many samples and lengthy simulations are needed to lower this noise floor and evaluate the signal harmonics. We present here a method to estimate the quantization noise, remove it from the SDM bitstream, and enable the reduction of the samples needed to evaluate the SDM linearity. By applying the proposed technique to a Simulink®model of a 4th-order SDM, the accuracy of the linearity estimation is kept unchanged using 5000x less bitstream samples. This method enables a significant reduction of SDM verification time that in turn can be used to improve the statistical coverage of design over parameter variability.

In this work, a test chip for a 32 channel ultrasound imaging digitizer for intra-cardiac echocardiography is presented. The focus of this design is on area- and power efficiency, as well as multi-purpose usage for various catheters. It contains 32 individual analog front-ends and 12 bit SAR ADCs operating at 40MS/s to enable off-chip digital beamforming. The analog front-end is programmable in power, bandwidth, gain and can be partially bypassed. The front-end bypass and slew-rate can be dynamically adjusted to save power during a receive period. On-chip supply regulation is included, which can be duty-cycled between receive periods to power down the system and save power. This leads to a power supply consumption between 4.5 and 14.1mW when always on, or between 0.37 and 1.15mW when duty-cycling at an 8% ratio. When operating at maximum power, an SFDR of 57.5dB and SNR of 56.1dB are achieved.The ADC performance can optionally be improved by clocking the array in 4 separate clock phases, resulting in lower peak currents, less power supply disturbance and an overall linearity improvement of 6dB. The 32 channel array occupies 1mm2 including decoupling capacitance, combining low area and low power operation.

This paper presents a high impedance, low noise, and low offset Analogue Front-End (AFE) designed to readout biosignals using non-contact electrodes. The circuit is fabricated in an amorphous InGaZnO (a-IGZO) technology. An autozeroing technique is used to reduce both 1/f noise and AFE offset while minimizing the charge required from the input, leading to a high input impedance. The AFE circuit makes use of two voltage buffers operated in a ping-pong configuration to ensure a continuous time operation. Measurement results reveal that, when autozeroing each 100μs, the AFE input impedance reaches 250MΩ at 50Hz, which is about 6x larger compared to the current state-of-the-art in large-area electronics. The Signal-to-Noise ratio estimated for non-contact electrodes with a 200MΩ series impedance remains above 20dB, while achieving a bandwidth of 1kHz, a power consumption of 0.22mW and an area per channel of 2.94mm2. Thanks to its versatility, the proposed AFE architecture in combination with the mechanical properties offered by the TFTs on foil, can be exploited to develop a new generation of wearable patches that are conformable, lightweight, and cost-effective. These devices could be employed in home health-monitoring applications to acquire biosignals such as sEMG (surface electromyography), while providing a great level of comfort to the patient.

This paper proposes an input range boosting technique for successive-approximation-register (SAR) analog-to-digital converters (ADC). By performing a pre-comparison and switching the DAC accordingly, the input range of a SAR ADC can be doubled with limited power and area overhead. This effectively improves the power efficiency by relaxing the noise requirement and improves the area efficiency by using less DAC capacitors. A prototype ADC is fabricated in 65 nm CMOS and occupies an area of 0.0033 mm2. It consumes$34.06\ \mu\mathrm{W}$at 10 MHz sampling rate from a 1 V supply. The measured SNDR is 62 dB for a 5 MHz bandwidth, resulting in a Walden figure of merit ($\text{FoM}_{W}$) of 3.28 fJ/conversion step.

This work presents a reconfigurable delay and redundancy technique, which relaxes the reference driver requirements for a charge-redistribution SAR ADC. By selectively adding delay to the most critical SAR cycle, the overall speed of the ADC is only slightly degraded, while the output impedance of the driver or the amount of decoupling capacitance can be reduced substantially. In a simulated 10-bit 10 MS/s SAR ADC prototype, the proposed technique reduces the decoupling capacitance by 16× while maintaining 59.2 dB SNDR and 71.2 dB SFDR at a power consumption of $32 \mu \mathrm{W}$. The estimated area is 0.002 mm2including decoupling capacitors.

An ultra-low power, energy efficient, and versatile resistive sensor interface for energy constrained internet-of-things applications is presented. The sensor interface includes an efficiently duty-cycled current digital-to-analog converter (I-DAC) and an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC), which enables a fully-dynamic operation. A fast start-up circuit is used in the duty-cycled I-DAC to speed up the start-up procedure and to minimize the energy consumption. A system-level correlated double sampling (CDS) technique is employed to suppress ADC offset and 1/$f$noise. To tackle the limited robustness against supply and temperature variations observed in a previous implementation of the sensor interface, a system-level ratiometric measurement (SRM) approach is employed in an updated design, which is described here in detail. The chip is fabricated in 65nm CMOS technology. Thanks to the all-dynamic nature, measurement rates from 0.1S/s to 12.5kS/s can be supported with an inherent scaling of power over 3 orders of magnitude. A reported lowest power consumption of 0.32nW is achieved at 0.1S/s. Adaptable resolution with efficient scaling of power can also be achieved by adjusting sensor interface settings and/or using oversampling and averaging. The achieved figure-of-merit (FoM), which ranges from 98 to 552fJ/conv-step is also the lowest among prior designs. Thanks to the SRM approach, only 3.6%/V and 21ppm/$^\circ \text{C}$supply and temperature sensitivity are obtained, respectively.

This paper presents an ultrasound rangefinder system able to find relative distances among energy-constrained sensor nodes. The nodes build a swarm that is operated in collision and multipath rich environments. A new distance measurement technique combining Wake-up and Frequency Modulated Continuous Wave (FMCW) is proposed to enable the ranging while neglecting the echoes from passive reflectors in the environment. The building blocks of the sensor nodes comprise a transmitter, a wake-up receiver, and a ranging receiver, all implemented in a 65 nm CMOS technology. The transmitter includes two switched-capacitor converters and an output multiplexer to generate a four-level driving signal and broadcast either a wake-up sequence or a digitally synthesized ultrasound Chirp. The transmitter dissipates 0.43 μJ and 0.82 μJ to broadcast the wake-up signal and the Chirp, respectively. A mixer first architecture is exploited in the wake-up receiver to reduce the always-on power consumption of the nodes. The ranging receiver uses a heterodyne architecture suited for the FMCW. The power consumption of the wake-up receiver and ranging receiver is 23.6 nW and 0.56 μW, respectively. The proposed rangefinder is experimentally characterized up to a 1 m distance in air and dissipates 1.25 μJ per measurement, achieving a resolution of 18.7 mm at 0.55 m.

This paper presents a digitally assisted tunable high pass filter for biomedical applications, implemented using unipolar a-IGZO TFTs manufactured on a flexible substrate. The proposed system is based on a master-slave approach. It takes advantage of the signal attenuation experienced in a high pass filter when a reference sinusoidal signal with a frequency lower than the cut off frequency is applied. The signal attenuation is monitored and a feedback loop automatically controls the small-signal resistance in the master and slave filters to obtain a specific signal attenuation, which in turn sets the passband frequency of the high pass filter. The presented approach is not only useful for setting a sub Hz cut off frequency but it is shown to be effective in counteracting parameter and supply voltage variations. The method presented in the paper can be also applied to Silicon biomedical circuits.

A Process Design Kit (PDK) for gravure-printed Organic Thin-Film Transistor (OTFT) technology is presented in this paper. The transistor model developed in the PDK enables an accurate prediction of static, dynamic and noise performance of complex organic circuits. The developed Electronic Design Automation (EDA) tools exploit an adaptive strategy to improve the versatility of the PDK in relation to the advancements of the manufacturing process. The design and experimental characterization of a Charge Sensitive Amplifier is used to demonstrate the effectiveness of the PDK. The availability of a versatile and accurate Process Design Kit is expected to enable a reliable design process for complex circuits based on an organic printed technology.

This paper proposes a technique to optimize dynamically the efficiency of hybrid switched capacitor converters, while changing their output voltage/current. Pulse width modulation can be used to change the output current in LED drivers based on hybrid converters. However, changes in duty-cycle cause a reduction in efficiency due to the increasing output resistance of the associated switched capacitor converter. The proposed solution re-configures dynamically the ratio among the flying capacitors and the size of the switches in the power train to minimize the output resistance in different duty-cycle ranges. Transistor level simulations, using 180nm CMOS technology, show the benefits of this technique in a 3:1 Dickson step-down hybrid capacitive LED driver using three duty-cycle optimization regions. A better efficiency and flatter output resistance over a variable conversion ratio was achieved with up to 8% efficiency improvement in this case study, without increasing the area occupied by power switches and flying capacitors.

The Phoenix1project aims to develop a new approach to explore unknown environments, based on multiple measurement campaigns carried out by extremely tiny devices, called agents, that gather data through multiple sensors. These low power and low resource agents are configured specifically for each measurement campaign to achieve the exploration goal in the smallest number of iterations. Thus, the main design challenge is to build agents as much reconfigurable as possible. This paper introduces the Phoenix project in more details, and presents first developments in the agent design.

This paper proposes a multiple-channel frontend system with current reuse for fetal monitoring applications. The structure and specifications of the proposed frontend system are determined while taking into consideration the algorithms used for fetal electrocardiogram (fECG) detection. Two amplifier topologies based on a middle rail current source/sink (MCS) are proposed for fECG and electrohysterogram (EHG) recording. The proposed amplifiers explore power optimization in both current and voltage domain and thus achieve a better effective noise efficiency factor (NEF) while providing multiple-channels. The frontend system is designed in a 0.18μm CMOS process. Simulation results show that the frontend system provides 3 fECG and 4 EHG recoding channels with a total power consumption of 3.1μW. The IA for fECG monitoring achieves an equivalent NEF of 1.17/1.21 for low noise and low power settings respectively.

This paper proposes a low-power noise scalable instrumentation amplifier (IA) for fetal monitoring applications. The noise specification of the IA is made adaptive to the peak-peak value of the fetal electrocardiography (fECG) signal, which varies for different gestational age and measurement settings. Contrary to the currently available point solution IAs, the proposed IA is scalable for a noise range from 30nV/VHz to 250nV/VHz while consuming 15μW to 1μW respectively. A new IA architecture is proposed to achieve a better noise efficiency factor (NEF), while allowing noise scalability. The IA is designed in TSMC 0.18μm CMOS process. Simulation results show that the IA achieves a NEF of 3.4 to 5.5 over the noise scalable range, a CMRR of 100dB, and an input impedance (Zin) of 1GO.