This paper describes the delay calculation method and the accuracy analysis of its interpolation for CMOS ASIC libraries which contain cell-based primitives and memories to be used during the pre-layout design phase of logic simulation, timing verification, and logic synthesis. The delay calculation method addressed in this paper is specified as IEC CDV 61523-2 standard which consists of the estimation of wire capacitance, and the delay calculation method based on a table look-up. Although the input to the delay calculator is net list and library parameters, the delay parameter part of the library has not been standardized because of its strong dependency on the delay calculation method. We, IEC/TC93/WG2/ALR group, specified it based on the EIAJ work. In IEC CDV 61523-2, we specified in detail a table look up calculation formula for CMOS ASIC library using a linear interpolation in the triangular area which is more accurate than the bilinear interpolation. In this paper, we overview the specification and provide the mathematical background for the interpolation.

Article Free Access Share on Design methodologies for consumer-use video signal processing LSIs Authors: Hisakazu Edamatsu Semiconductor Research Center, Matsushita Electric Industrial, Co., Ltd., Moriguchi, Osaka 570, Japan Semiconductor Research Center, Matsushita Electric Industrial, Co., Ltd., Moriguchi, Osaka 570, JapanView Profile , Satoshi Ikawa Semiconductor Research Center, Matsushita Electric Industrial, Co., Ltd., Moriguchi, Osaka 570, Japan Semiconductor Research Center, Matsushita Electric Industrial, Co., Ltd., Moriguchi, Osaka 570, JapanView Profile , Katsuya Hasegawa Semiconductor Research Center, Matsushita Electric Industrial, Co., Ltd., Moriguchi, Osaka 570, Japan Semiconductor Research Center, Matsushita Electric Industrial, Co., Ltd., Moriguchi, Osaka 570, JapanView Profile Authors Info & Claims DAC '96: Proceedings of the 33rd annual Design Automation ConferenceJune 1996 Pages 497–502https://doi.org/10.1145/240518.240613Published:01 June 1996Publication History 0citation123DownloadsMetricsTotal Citations0Total Downloads123Last 12 Months4Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Proposes a new algorithm of estimation and compensation of the error effect for rounding in the case of implementation of division and square root using the Newton-Raphson method. The authors analyze the error of the hardware system to confirm the condition of the implementation with respect to this algorithm. Next, they describe in detail how to compensate the error by using this algorithm. Finally, they show that the hardware components for this algorithm, the direct rounding mechanism in the recode circuit and the sticky digit generating circuit, can be realized simply by improving the redundant binary representation multiplier. The number of increasing cycles for this new algorithm is only one, and the rounding result using this algorithm satisfies IEEE Standard 754 rounding perfectly.>

A high speed multiplier and divider for MOS LSI based on a new algorithm is presented. When we implement the multiplier and the divider in LSI, the features such as high speed operation, small number of transistors and easy layout are the most important factors. A computational algorithm using a redundant binary representation has several excellent features such as high speed addition operations. We improved the algorithm and the method of implementation, and designed an advanced multiplier and divider with the above mentioned features. We expect mat our multiplier and divider are excellent compared with multipliers using the Booth algorithm and the Wallace tree, and with divider using the SRT method, respectively.