The best-known IEEE standards in the test domain (JTAG 1149.1 and IJTAG 1687) have enabled the automation of the logic aspects of testing. However, the electrical aspects and the whole world of mixed-signal test are still left to ad-hoc solutions to be developed on the fly by design and test engineering teams. As a result, mixed-signal test consumes a disproportionate share of test time and development effort. The P1687.2 extension has set out to address analog test needs. Some of its concepts will be adopted by the next edition of the digital base standard IEEE 1687.This paper describes new methods for joining analog and digital test properties and behaviour with a consistent description, spanning from seemingly trivial aspects like bidirectionals and relays to co-existence with the full range of analog stimuli and measurements. True to the IJTAG mission of retargeting test procedures from IP to chip-level and beyond, mixed-signal test intent can be captured in a new standard language (PDL2) for a design block, which is instantiated multiple times, and retargeted across hierarchy levels, resolving the conflicts for limited resources like test pins and test buses.

This volume contains the papers presented at the 2023 International Test Conference, held from October 10 - 12 at the Disneyland Hotel, Anaheim California. ITC is the world's premier conference dedicated to electronic test. This year's ITC continued with its mission to play a unique role as an information sharing forum, where the wide range of its offerings allows ITC participants to learn, network and conduct business. This year's program included a top-notch technical program, vibrant exhibitors, informationpacked tutorials, interactive technical panels, three focused workshops, as well as the all-important networking that these events provide. The technical program was designed to optimize personal interactions on all levels.

Following IEEE Standard Association (IEEE SA) guidelines, actively used standards should be revised every ten years. IEEE 1149.1 was published in 2013, while IEEE 1687 was published in 2014. Hence, both standards were revisited, and for both, it was determined that a refresh would be beneficial to the community. Consequently, working groups were established and are ongoing. Here, we outline their agenda and progress. Since 2014, other standards that based on 1687 were initiated. In this paper IEEE P1687.1, IEEE P1687.2, and P2654 report on their progress. An in-depth update of IEEE P1687.1 was given during the International Test Conference (ITC) in 2022.

Modern integrated circuits used in automotive, industrial, consumer, and IoT (Internet of Things) applications often have limited pin counts. Despite this, these devices can be complex, with significant digital and analog content. These features require rigorous testing to address the quality and reliability requirements of these applications. Because of their limited pin count, a TAP controller interface is often not an option or the TAP controller interface itself may not be an option for other reasons, such as die area. Further, the increasing number of IP based designs, along with the increasing availability of IP cores can result in an IP being integrated deep inside a design. Designers, DfT engineers, and test engineers are facing increasing challenges with the integration and testability of IP in their chips. They also have the task of having to test through interfaces that may change depending on the needs of the customers. IEEE P1687.1 is working on processes that will provide a means for automating communications through non-TAP interfaces, making these types of products ideally suited for the techniques currently under consideration for standardization. This paper, reviews the latest topics being discussed by the working group, including the framework for communicating through these interfaces. It discusses how proto buffers (protobufs) can be used to help bridge the gap between a host controller, like an ATE, and an IJTAG network. The approach leverages the concept of Remote Procedural Calls (RPCs) from the IT space and the integer bit vector (intbv) concept from myHDL to support communications through interfaces and between subroutines handling retargeting and handling control of the interface. A model is presented for evaluating the options and various criteria are reviewed with respect to the framework. The paper also explores debug concerns and potential security issues and how those can be addressed.

The industry is moving forward with non-TAP, chip-level interfaces driving IEEE 1687-2014 networks. Recent literature not only describes such interfaces, like I2C and IEEE 1149.7 variants, but also demonstrates that such interfaces to IEEE 1687 are already proven in silicon. Common to those implementations is the need for "private" extensions of IEEE 1687 to make it support non-TAP interfaces. The goal of IEEE P1687.1 is to directly support non-TAP interfaces. In this work, we summarize the thought progression from IEEE 1687's data register callbacks to IEEE P1687.1's transfer function, which allows alignment with IEEE P2654, and possibly IEEE P1687.2.

This paper introduces a standards-based framework which enables two types of test re-use: direct re-use of test patterns written for low-level components of a system, and access by high-level tests of test features embedded within the low-level components. The underlying mechanism for both is the encapsulation, retargeting, and transformation of test procedures through successive layers of hardware interfaces, as codified in two standards being developed by IEEE Working Groups (P1687.1 and P2654). Examples demonstrate the steps in the process and illustrate both the challenges and opportunities of this approach.

Many modern devices have a very limited number of digital pins, yet they are often quite complicated internally. These ICs can't afford the luxury of a traditional JTAG TAP controller and the associated 4 or 5 extra pins. Nonetheless, these devices often contain significant digital and analog content. This complexity makes testing very challenging. Moreover, IP-based design often results in having an instrument buried deep inside a device, the access of which requires transitioning through multiple interfaces and controllers. This is exactly the situation DfT and test engineers face when designing and implementing tests for embedded IP. Techniques proposed for IEEE P1687.1 enable an automated mechanism for retargeting tests through a variety of non-TAP interfaces. This makes these products ideal candidates for IJTAG and IJTAG.1 test strategies. In this paper, we focus on demonstrating how on-chip test functions and IP can be successfully controlled and observed through non-TAP interfaces by controlling data flow using RVF (Relocatable Vector Format) and callbacks. This unique and novel approach ensures tool interoperability and allows tools to model interfaces in the same way, without requiring special descriptions for each one. The paper proposes an automated tool flow for retargeting the tests and provides example implementations on several specialized designs including I2C, an In-System TAP, IEEE 1149.7like interface, and a security block.

IJTAG (IEEE 1687) has proven to successfully address the challenge of test integration for “digital instruments” in digital systems on chip (SoCs). Yet, beyond SoCs, mixed signal IP presents an even bigger obstacle. This is particularly true for so-called Big-A/little-d chips, which have a significant number of analog IP blocks whose integration makes meeting fast test development cycle time requirements, from silicon to test program readiness, a challenge. Also, these chips rarely include a JTAG TAP for access to test data registers (TDRs) on scan chains. Instead, they have very simple serial interfaces, like $I^{2}C$ or SPI, and these are the only form of communication with the system and, consequently, with the ATE. This paper demonstrates the principles of test generation for a Power Management Integrated Circuit (PMIC) using the Procedure Description Language (PDL) of the P1687.2 standard. The authors show how a test procedure for a medium complexity analog block, an LDO (Low Drop Out regulator) can be retargeted and transformed to the chip top level and from there to the ATE test programs. The typical test infrastructure of the PMIC is modelled in ICL, the InterConnect Language of the IEEE standards 1687, P1687.1 and P1687.2. In addition, the employment of the P1687.1 callbacks enables transparent access of test registers via transformations through the serial communication interface.

The IEEE 1687-2014 standard introduced the concept of portable, retargetable tests for digital circuits and taught how to apply them via a JTAG Test Access Port. Two follow-on standardization efforts address the topics of portable, retargetable analog tests (IEEE P1687.2) and applying analog or digital tests via non-TAP interfaces (IEEE P1687.1). IEEE P2427 complements these efforts by defining how to measure and report coverage of analog tests. This session will use a running example to show how all three initiatives play together.

In this IP session, there will be 3 presentations focusing on how to increase the in-field quality level of A/MS devices. The 1stpresentation will discuss using optical inspection data with electrical test data such that the combined data can be used to further screen out potentially bad devices that would have normally passed electrical testing. The 2ndpresentation discuses using a top level fault injection method to determine the ASIL levels in the ISO26262 standard. The 3rdpresentation will discuss the current progress of the P2427 Standardized Analogue Test Coverage Working Group and how this standard can be used to increase quality levels of A/MS devices.

Modern SOCs may be composed of hundreds of individual physical modules, referred to as tiles. The total number of scan channels servicing these tiles often greatly exceeds the number of SOC device pins available to connect those channels to test equipment. Traditional reliance on a small number of pin-to-channel test mode configurations, predetermined in hardware, results in inefficient scan data bandwidth utilization. Herein is presented a flexible switching network called the Scan Routing Fabric (SRF) which can connect any set of tiles' scan channels to available SOC pins in order to facilitate optimal scheduling of tile patterns by box-packing algorithms. Other planned improvements to be integrated with the SRF, such as MICTAM, and independent mode are also discussed. Results from deployment on the latest AMD chip show a one-third reduction in test time.

Through four use cases with examples, we describe how IEEE 1687 can be extended to include analog and mixed-signal chips, including linkage to circuit simulators on one end of the ecosystem and ATE on the other. The role of instrumentation, whether on the tester or on the device itself, is central to analog testing, and conveniently also the focal point of IEEE 1687. We identify enhancements to the modular netlist and test languages (ICL and PDL) to facilitate the description of the components involved in analog tests as well as the content of the tests themselves.

An analog test bus and serial digital access to ADC and DAC parallel ports are two widely used analog DFT techniques. Unfortunately, they cannot be described in a standard way that could facilitate automatic test pattern generation (ATPG). Furthermore, serially accessing an ADC/DAC is typically too inefficient for periodic sampling for various reasons, but mostly because of the capture/update-then-shift sequence used in IEEE 1149.1, 1500, and 1687. This paper shows that if a small amount of digital circuitry is added to each accessed ADC/DAC parallel port, they could be described in IEEE 1687 instrument connection language (ICL) to facilitate optimally efficient streaming access to the parallel ports. Furthermore, this could be automated by adding our proposed “iStream” as a new 1687 procedural description language (PDL) command. We provide examples of how it would be used, along with evidence to show it can provide more efficient (up to 2X, or more) serial access rate to ADCs and DACs than previous automatable approaches.

This paper provides an overview of a flow to generate and apply cache-resident self-test (CReST) patterns on a CPU as an alternative to deterministic functional patterns. This paper also compares CReST patterns against deterministic functional patterns, including the results of a case study of applying both CReST and deterministic functional patterns on commercially available AMD x86 processors in highvolume production. The experiment indicates that CReST patterns are an effective substitute for functional patterns.

The high-technology industry in general, and its infrastructure aspects (such as testing) in particular, have recently garnered skepticism with respect to the ability to continue to innovate. This talk will analyze the sources of such criticism, along with possible antidotes, especially the role of “magical thinking” (as popularized in the recent biography of Steve Jobs). The distinction between fantasy and vision will be explained, with examples drawn from several aspects of practical test engineering, both past and future. The audience will be challenged (and hopefully inspired) to tackle the problems faced by our industry with an approach which is at the same time both visionary and pragmatic.

As chips are getting increasingly complex, there is no surprise to find more and more built-in DFX. This built-in DFT is obviously beneficial for chip/silicon DFX engineers; however, board/system level DFX engineers often have limited access to the build in DFX features. There is currently an increasing demand from board/system level DFX engineers to reuse chip/silicon DFX at board/system level. This special session will discuss: What chip access is needed for board-level for test and diagnosis? How to accomplish the access? Will IEEE P1687 and IEEE 1149.1 solve these problems?

A novel slave clock-gating technique in [5] is designed to save power when the master and slave latches of a low-power flip-flop reach certain correlated states (e.g., both latches are at logic 0 or 1). Testing this clock-gating circuit is essential for power-sensitive applications, but is also very challenging. This is because power consumption increase is its only defective behavior, and it involves cell internal states, both of which are unfriendly to general automatic test-pattern generation (ATPG). This paper proposes an innovative method to test the slave clock-gating circuitry structurally with slight modification of the flop cell. The implementation on a two-latch version of a level-sensitive scan design (LSSD) flip-flop and its capability of extending to other types of flip-flop cells are presented.

Have you ever had the problem of trying to determine what compression technique to use from which tool vendor and what to do if any of that changes during the design flow? This paper will present a DFT architecture and automation solution that provides flexibility for designs using scan compression. It combines generic and proprietary techniques to enhance testability, reduce design risk, and improve development time. Data and results for the use of this technique in a microprocessor chip will also be presented.

The use of low-cost structural Fmax measurement as a replacement for in-system Fmax measurement for speed binning has been aided by the use of a data-learning approach that can be used to build a reliable system Fmax predictor given structural Fmax. This paper uses industry test measurements to demonstrate why a data-learning approach for correlation is better than simple correlation approaches, how to select the most relevant structural Fmax, and how the proposed methodology works on multiple lots.

A technique is described for testing the I/O interfaces of a microprocessor through the use of cache-resident self-test. Experimental results show that this test application method executes much faster than traditional scan-based testing for both characterization and production versions of the tests. The addition of on-chip post-processing of test results further enhances the speedup. The method is compatible with low-cost testers.

The use of embedded test instrumentation in ASIC designs has changed dramatically over the last decade. This is due to a variety of forces that affect the semiconductor industry. Unfortunately, processes surrounding test creation and validation this instrumentation has become significantly more complicated in recent years. IEEE P1687, which is now nearing completion and ballot, addresses these issues and makes the access and control of embedded instruments nearly automatic. This poster session will illustrate the latest innovations in the standard.

As cost pressures on electronic products continually increase, the urge to trim investment in test-related circuitry, activity, and equipment increases correspondingly. Not only can this strategy backfire if taken too far, but it also ignores the opportunity for test to actually add value to products. This presentation will examine the positive role that test can play and give audience members a set of guidelines to take back to their own companies so that they can perform their own analyses. Numerous examples from a variety of different electronic industries show a wide range of possible solutions.

The application of SOC-style test partitioning to a monolithic microprocessor design results in considerable benefits, including simpler and faster ATPG, reduced ECO impact, faster debug, and, most surprisingly, reduced test application time. These results challenge the orthodoxy that flat, top-level ATPG is the best method to produce an optimal pattern set. The granularity of the partitioning was the key factor in achieving the results: a 33-element partition of the AMD™ Athlon CPU chip resulted in better than a ∼80% reduction in test time compared to a flat model of the entire chip. This paper describes the ATPG experiments and quantifies the design overhead required for implementing wrapper cells at partition boundaries.

The effort to standardize a methodology for accessing embedded instrumentation as IEEE PI687 continues to progress. This paper captures the current state of mind of the IJTAG working group with respect to the framework built to date and presents a discussion of other issues on which decisions are pending. The key elements of an architectural description language, a procedural language, and a hardware interface scheme are all taking shape, but still have many details to complete. Since this is a snapshot taken during the standard development process, the final form of the draft standard may differ from what is described here; any feedback to the working group is welcome

The past two decades have seen a steady stream of challenges and responses in the test field. This paper surveys selected key problems and the progression of their solutions, in both topical and intrinsic aspects, with the aim of performing a meta-analysis of the nature of test innovation. The significant track record of success demonstrated by the industry will be put under serious pressure as technology advances

The performance of high-speed serial data links, along with the architectures of the transmitter and receiver circuitry used on either end, has led to increasing difficulty in applying traditional test and measurement techniques to characterize these channels. One solution, explored in this work, utilizes stimulus generation and response analysis circuitry embedded in the devices driving and receiving the links to perform a variety of tests and measurements that match and even exceed those possible with traditional instruments, as actual silicon results demonstrate. The access to this embedded measurement circuitry is provided via the IEEE std. 1149.1 test access port by use of a possible prototype for the draft IEEE P1687 (IJTAG) standard. This access mechanism is explained and its wider applications for test and debug are explored

The widespread use of the IEEE 1149.1 standard test access port as the interface for not only boundary scan but also for access to device-internal test features has led to a highly useful but highly fragmented opportunity for the test community. The need for a standard description of internal test features and protocols is elucidated, and the framework for the extension of the boundary scan standards as launched by the ad hoc IJTAG working group is described

Delay fault testing via AC scan is shown to suffer from test application problems that, if not accounted for, will cause a reduction in test quality. The problem of clock period stretching is demonstrated, and a novel circuit for calibrating this effect is described. Guidelines for AC scan test application on the tester to improve the quality of AC scan tests are presented, along with results from several large ASICs.

A minimally invasive solution for adding boundary scan to high-speed I/O circuits is described. The insertion of boundary scan registers on the transmit side is done in the lower-speed parallel domain, while the boundary scan registers on the receive side is done using the techniques described in IEEE standard 1149.6 in the high-speed serial domain. Special clocking requirements are described, and results from actual silicon testing are presented that demonstrate negligible impact on functional performance while maintaining compliance with the both 1149.1 and 1149.6 standards.

This paper provides proof of concept for the newly-approved 1149.6 standard by investigating the first silicon implementation of the test receiver. EXTEST and EXTEST/spl I.bar/PULSE tests were applied to functional channels as well as channels with a set of externally-induced hard defects. All valid signals were correctly received, and all defects were detected, thus validating both 1149.6's anticipated backwards compatibility with 1149.1 and fault coverage. Mission-mode tests showed no performance degradation due to the test circuits. Characterization across PVT of the test receiver suggests 1149.6's robustness with respect to noise.

Localized delay defects, like resistive shorts, resistive opens, etc., can be effectively detected by testing the longest testable path through each wire (or gate) in the circuit. Such a delay test set is referred to as a longest-path-per-wire test set. In this paper we study test data volume and test application time reduction techniques for such tests based on the Illinois scan architecture. We present a novel ATPG flow to quickly determine longest-path-per-wire test sets under constraints imposed by the Illinois scan architecture. Results of experiments on ISCAS sequential circuits are presented. On an average we achieve a test data volume reduction of 2.79X and number of test cycles reduction of 3.28X for robust path delay, tests (as compared to the case without Illinois scan). The corresponding numbers for non-robust tests are 3.58X and 4.24X.

The use of AC coupling capacitors on high-speed interconnects prevents the use of traditional DC-based boundary-scan techniques to test for board manufacturing defects. A solution is provided by a novel scheme that makes use of frequency discrimination using simple digital circuits that are easily integrated with the 1149.1 boundary-scan standard. Simulation results are presented which show the effectiveness of this method, and its robustness and scalability are compared with alternative solutions.

Delay fault test application via enhanced scan and skewed load techniques is shown to allow scan-based delay tests to be applied that are unrealizable in normal operation. Rather than higher coverage being a positive feature, it is shown to have negative impact on yield and designer productivity. The use of functionally justified tests is defended by both a motivating example and data from benchmark circuits. Implications on overhead, yield, timing optimization, and test debug are discussed.

The distortion of test coverage statistics by overly simplistic circuit and fault models is explored. It is shown that the artificially high single stuck-at coverage reported on traditional gate-level models results in the omission of test patterns essential to achieve full coverage. The problem lies not directly with the fault model, but instead with the gate models and test generator assumptions used. The necessity of two-pattern tests is demonstrated on simple library cells, and the stuck-at coverage improvement measured on benchmark circuits is shown to average 33%. The need for a superior fault model is explained.

This paper describes a method for testing non-scanned embedded latch-based FIFOs on an otherwise full-scan chip by using the scan registers that surround the FIFO and sharing the test application time with the other ASIC scan tests. The technique of excising the FIFOs from the ASIC to allow separate and effective test generation for each is explained, as is the process used to merge the two tests back together for efficient test application. Results are presented for three example ASICs which indicate that the method is both efficient and thorough.

This paper presents a switch-level simulation-based method for estimating quiescent current values. The simulator identifies transistors that are in the proper state to experience leakage mechanisms. This information is combined with data about both the size of these transistors and various process parameters in order to calculate the actual I/sub DDQ/ value. SPICE simulation results are presented on a variety of circuits to both calibrate the simulator, and to demonstrate state, time and sequence dependencies of circuits. Some preliminary results are also given for an actual production chip.

As ATPG algorithms become more efficient at minimizing the number of patterns required to detect SSA faults, dependence on incidental detections of nontarget static defects will become increasingly less prudent. Even more importantly, tests for delay defects require at-speed clocks and are absolutely not covered by static SSA tests, even incidentally and it is expected that delay defects will become increasingly common in synthesized circuits. Interestingly, the SSA fault model, with only minor extensions, can still serve as the foundation for ATPG and fault simulation tools for these more detailed fault models. Additional constraints can be placed on these tools to force them to meet the extra excitation requirements (like forcing values on the two nodes at a bridging site, or clocking two opposite values at speed through a delay fault site), while still maintaining the relative computational tractability associated with the SSA model. To that extent, future test advances may be a matter of "buying time" for the SSA model.

The full scan design methodology undisputably has many benefits throughout the process of ASIC and system design and during the life cycle of a product that may justify its use, but it has some very definite costs as well. These include larger die area, reduced circuit performance and the fact that there are usually a number of memory elements which are not scanned. It is suggested that partial scan be useful in augmenting the test coverage on critical portions of high performance chips, and that it can also serve as the basis for an area-efficient design methodology on any chip. Partial scan is another facet of the continual improvement process in IC design. As new developments in flip-flop selection and sequential ATPG are integrated into design flows, partial scan can become as push-button as full scan now is. When coupled with a design methodology driven by timing analysis and synthesis, partial scan could well be the key to producing designs that are optimized for performance, area, and testability.

This paper identifies the two key factors involved in obtaining accurate bridging fault simulation results and presents a hybrid technique that maximizes both the speed and accuracy of bridging fault simulation for gate-level standard cell designs. Both combinational and sequential circuits are studied and the results are compared with several other bridging fault simulators.>